✓ Fi.CI.BAT: success for Geminilake pipe CSC (rev2)

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== Series Details ==

Series: Geminilake pipe CSC (rev2)
URL   : https://patchwork.freedesktop.org/series/18596/
State : success

== Summary ==

Series 18596v2 Geminilake pipe CSC
https://patchwork.freedesktop.org/api/1.0/series/18596/revisions/2/mbox/


fi-bdw-5557u     total:247  pass:233  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:247  pass:208  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:247  pass:225  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:79   pass:66   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:247  pass:227  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:247  pass:222  dwarn:4   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:247  pass:215  dwarn:0   dfail:0   fail:0   skip:32 

66c972ab613b1f1d659f413f850047077f3363f0 drm-tip: 2017y-01m-27d-08h-06m-49s UTC integration manifest
40b3da38 drm/i915: Merge BDW pipe gamma and degamma table code
28b9d12 drm/i915/glk: Enable pipe CSC
81389e6 drm/i915/glk: Program pipe gamma and degamma tables
4a0d57f drm/i915: Split broadwell_load_luts() into smaller functions
446ac15 drm/i915/glk: Plane color correction register changes
9a2501c drm/i915: Disable plane gamma in SKL+ sprite planes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3619/
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