On Thu, Jan 26, 2017 at 01:24:23PM +0200, Ander Conselvan de Oliveira wrote:
> Split the logic for progamming each LUT out of broadwell_load_luts(), so
> we can reuse part of it for geminilake.
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_color.c | 43 ++++++++++++++++++++++++++++----------
> 2 files changed, 33 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9947354..06bbe55 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8171,6 +8171,7 @@ enum {
> #define PAL_PREC_10_12_BIT (0 << 31)
> #define PAL_PREC_SPLIT_MODE (1 << 31)
> #define PAL_PREC_AUTO_INCREMENT (1 << 15)
> +#define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0)
> #define _PAL_PREC_DATA_A 0x4A404
> #define _PAL_PREC_DATA_B 0x4AC04
> #define _PAL_PREC_DATA_C 0x4B404
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 34952d0..82a3bc9 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -340,20 +340,12 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
> hsw_enable_ips(intel_crtc);
> }
>
> -/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> -static void broadwell_load_luts(struct drm_crtc_state *state)
> +static void bdw_load_degamma_lut(struct drm_crtc_state *state)
> {
> - struct drm_crtc *crtc = state->crtc;
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> - struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> - enum pipe pipe = to_intel_crtc(crtc)->pipe;
> + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> + enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>
> - if (crtc_state_is_legacy(state)) {
> - haswell_load_luts(state);
> - return;
> - }
> -
> I915_WRITE(PREC_PAL_INDEX(pipe),
> PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT);
>
> @@ -377,6 +369,18 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> (v << 20) | (v << 10) | v);
> }
> }
> +}
> +
> +static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> + enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +
> + WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
> +
> + I915_WRITE(PREC_PAL_INDEX(pipe),
> + PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT | offset);
>
> if (state->gamma_lut) {
> struct drm_color_lut *lut =
> @@ -410,6 +414,23 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
> I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
> }
> +}
> +
> +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> +static void broadwell_load_luts(struct drm_crtc_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> + struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> + enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> +
> + if (crtc_state_is_legacy(state)) {
> + haswell_load_luts(state);
> + return;
> + }
> +
> + bdw_load_degamma_lut(state);
> + bdw_load_gamma_lut(state,
> + INTEL_INFO(dev_priv)->color.degamma_lut_size);
>
> intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT;
> I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT);
> --
> 2.5.5
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
