On Fri, 20 Jan 2017, Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> wrote:
> With GLK was introduced IS_LP.
> With this, we can use IS_GEN9 and IS_LP to put Skylake
> and Kabylake in the same bucket. The main intention is
> to simplify the if and else statements that gets added
> for every new platform.
>
> This approach proposes the idea to create a common bucket
> to put multiple platforms (SKL and KBL in this case)
> together. Another approach would be to introduce IS_GEN9_BC
> as suggested by Rodrigo, where _BC stands for Big Core.
I think we need to come up with an alias like IS_GEN9_BC(), although I'm
not convinced about that paraticular name. The current (FOO || BAR) for
specific FOO and BAR is *much* faster to read than the slightly
confusing (GROUP && !SUBGROUP).
One other comment inline.
> The i915_drv.c was let out of this patch on purpose
> because that is really a decision per platform, just like
> other cases where IS_KABYLAKE is different from IS_SKYLAKE.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/intel_color.c | 4 ++--
> drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++----------
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/intel_i2c.c | 4 ++--
> drivers/gpu/drm/i915/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 11 +++++------
> 12 files changed, 38 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index fa69d72..a4fdb9f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1224,20 +1224,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> - max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> + max_freq *= ((IS_GEN9(dev_priv) && !IS_LP(dev_priv)) ?
> GEN9_FREQ_SCALER : 1);
There's already superfluous braces to begin with, please don't add more!
Same all around.
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> - max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> + max_freq *= ((IS_GEN9(dev_priv) && !IS_LP(dev_priv)) ?
> GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> - max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> + max_freq *= ((IS_GEN9(dev_priv) && !IS_LP(dev_priv)) ?
> GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
> @@ -1814,7 +1814,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> if (ret)
> goto out;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq =
> dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
> @@ -1834,7 +1834,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> &ia_freq);
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(dev_priv, (gpu_freq *
> - (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
> + ((IS_GEN9(dev_priv) && !IS_LP(dev_priv)) ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> @@ -4444,7 +4444,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>
> sseu->slice_mask |= BIT(s);
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> sseu->subslice_mask =
> INTEL_INFO(dev_priv)->sseu.subslice_mask;
>
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 16c2027..fb2a7ee 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -702,7 +702,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> u32 tmp;
>
> - if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
> + if (!(IS_GEN9(dev_priv) && !IS_LP(dev_priv)))
> return;
>
> i915_audio_component_get_power(kdev);
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index d81232b..c1e6891 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -536,8 +536,8 @@ void intel_color_init(struct drm_crtc *crtc)
> } else if (IS_HASWELL(dev_priv)) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = haswell_load_luts;
> - } else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
> - IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + } else if (IS_BROADWELL(dev_priv) || (IS_GEN9(dev_priv) &&
> + !IS_GEMINILAKE(dev_priv))) {
> dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
> dev_priv->display.load_luts = broadwell_load_luts;
> } else {
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 66b367d..7c36423 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -445,7 +445,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
> if (IS_GEN9_LP(dev_priv))
> return hdmi_level;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
> hdmi_default_entry = 8;
> } else if (IS_BROADWELL(dev_priv)) {
> @@ -518,7 +518,7 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
> n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
> }
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> /* If we're boosting the current, set bit 31 of trans1 */
> if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
> iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
> @@ -572,7 +572,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
>
> hdmi_level = intel_ddi_hdmi_level(dev_priv, port);
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
>
> /* If we're boosting the current, set bit 31 of trans1 */
> @@ -1089,7 +1089,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>
> if (INTEL_GEN(dev_priv) <= 8)
> hsw_ddi_clock_get(encoder, pipe_config);
> - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> skl_ddi_clock_get(encoder, pipe_config);
> else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_clock_get(encoder, pipe_config);
> @@ -1150,7 +1150,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> struct intel_encoder *intel_encoder =
> intel_ddi_get_crtc_new_encoder(crtc_state);
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
> intel_encoder);
> else if (IS_GEN9_LP(dev_priv))
> @@ -1641,7 +1641,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
>
> level = translate_signal_level(signal_levels);
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> @@ -1658,7 +1658,7 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
> if (WARN_ON(!pll))
> return;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> uint32_t val;
>
> /* DDI -> PLL mapping */
> @@ -1714,7 +1714,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> intel_ddi_clk_select(encoder, pll);
> intel_prepare_hdmi_ddi_buffers(encoder);
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> skl_ddi_set_iboost(encoder, level);
> else if (IS_GEN9_LP(dev_priv))
> bxt_ddi_vswing_sequence(dev_priv, level, port,
> @@ -1784,7 +1784,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
> intel_edp_panel_off(intel_dp);
> }
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
> DPLL_CTRL2_DDI_CLK_OFF(port)));
> else if (INTEL_GEN(dev_priv) < 9)
> @@ -2157,7 +2157,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
> pll->state = tmp_pll_state;
> return NULL;
> }
> - } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + } else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> pll = skl_find_link_pll(dev_priv, clock);
> } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> pll = hsw_ddi_dp_get_dpll(encoder, clock);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index fcf8181..8acd7dc 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -189,7 +189,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
> * pair per subslice.
> */
> sseu->has_slice_pg =
> - (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) &&
> hweight8(sseu->slice_mask) > 1;
> sseu->has_subslice_pg =
> IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0f4272f..952d0b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5799,7 +5799,7 @@ static int skl_calc_cdclk(int max_pixclk, int vco);
>
> static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
> {
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
> int max_cdclk, vco;
>
> @@ -10666,7 +10666,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -15667,7 +15667,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> */
> found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
> /* WaIgnoreDDIAStrap: skl */
> - if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (found || (IS_GEN9(dev_priv) && !IS_LP(dev_priv)))
> intel_ddi_init(dev_priv, PORT_A);
>
> /* DDI B, C and D detection is indicated by the SFUSE_STRAP
> @@ -15683,7 +15683,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> /*
> * On SKL we don't have a way to detect DDI-E so we rely on VBT.
> */
> - if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> + if ((IS_GEN9(dev_priv) && !IS_LP(dev_priv)) &&
> (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
> dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
> @@ -16182,7 +16182,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> }
>
> /* Returns the core display clock speed */
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> dev_priv->display.get_display_clock_speed =
> skylake_get_display_clock_speed;
> else if (IS_GEN9_LP(dev_priv))
> @@ -16263,7 +16263,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> bxt_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> bxt_modeset_calc_cdclk;
> - } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + } else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> dev_priv->display.modeset_commit_cdclk =
> skl_modeset_commit_cdclk;
> dev_priv->display.modeset_calc_cdclk =
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e80d620..a806439 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -226,7 +226,7 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> if (IS_GEN9_LP(dev_priv)) {
> *source_rates = bxt_rates;
> size = ARRAY_SIZE(bxt_rates);
> - } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + } else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> *source_rates = skl_rates;
> size = ARRAY_SIZE(skl_rates);
> } else {
> @@ -1752,7 +1752,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> * clock for eDP. This will affect cdclk as well.
> */
> if (is_edp(intel_dp) &&
> - (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
> + (IS_GEN9(dev_priv) && !IS_LP(dev_priv))) {
> int vco;
>
> switch (pipe_config->port_clock / 2) {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index c92a255..b5fafd4 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2015,7 +2015,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> else if (IS_GEN9_LP(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 89fe5c8..2a0b98c 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -538,7 +538,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv,
> * If we enable FBC using a CFB on that memory range we'll get FIFO
> * underruns, even if that range is not reserved by the BIOS. */
> if (IS_BROADWELL(dev_priv) ||
> - IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + (IS_GEN9(dev_priv) && !IS_LP(dev_priv)))
> end = ggtt->stolen_size - 8 * 1024 * 1024;
> else
> end = U64_MAX;
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bce1ba8..a0ffaac 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -74,7 +74,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
> {
> if (IS_GEN9_LP(dev_priv))
> return &gmbus_pins_bxt[pin];
> - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> return &gmbus_pins_skl[pin];
> else if (IS_BROADWELL(dev_priv))
> return &gmbus_pins_bdw[pin];
> @@ -89,7 +89,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
>
> if (IS_GEN9_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bxt);
> - else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + else if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_skl);
> else if (IS_BROADWELL(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_bdw);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index c787fc4..4956681 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -178,7 +178,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> {
> bool result = false;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 249623d..ec1ca83 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5293,8 +5293,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
>
> dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
> - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> - IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if ((INTEL_GEN(dev_priv) >= 7) && !IS_LP(dev_priv)) {
> u32 ddcc_status = 0;
>
> if (sandybridge_pcode_read(dev_priv,
> @@ -5307,7 +5306,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> dev_priv->rps.max_freq);
> }
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> /* Store the frequency values in 16.66 MHZ units, which is
> * the natural hardware unit for SKL
> */
> @@ -5637,7 +5636,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> /* convert DDR frequency from units of 266.6MHz to bandwidth */
> min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
> max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
> @@ -5655,7 +5654,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> int diff = max_gpu_freq - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) {
> /*
> * ring_freq = 2 * GT. ring_freq is in 100MHz units
> * No floor required for ring frequency on SKL.
> @@ -6775,7 +6774,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> } else if (INTEL_GEN(dev_priv) >= 9) {
> gen9_enable_rc6(dev_priv);
> gen9_enable_rps(dev_priv);
> - if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> + if (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> gen6_update_ring_freq(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> gen8_enable_rps(dev_priv);
--
Jani Nikula, Intel Open Source Technology Center
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