On Wed, 18 Jan 2017, Manasi Navare <manasi.d.navare@xxxxxxxxx> wrote:
> v2:
> * Add all the other DP Complianec TEST register defs (Jani Nikula)
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> ---
> include/drm/drm_dp_helper.h | 58 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 0468135..ff03f8a 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -417,6 +417,64 @@
> #define DP_TEST_LANE_COUNT 0x220
>
> #define DP_TEST_PATTERN 0x221
> +# define DP_NO_TEST_PATTERN (0x0)
> +# define DP_COLOR_RAMP (0x1)
> +# define DP_BLACK_AND_WHITE_VERTICAL_LINES (0x2)
> +# define DP_COLOR_SQUARE (0x3)
The braces are unnecessary.
> +
> +#define DP_TEST_H_TOTAL_HI 0x222
> +#define DP_TEST_H_TOTAl_LO 0x223
> +
> +#define DP_TEST_V_TOTAL_HI 0x224
> +#define DP_TEST_V_TOTAl_LO 0x225
> +
> +#define DP_TEST_H_START_HI 0x226
> +#define DP_TEST_H_START_LO 0x227
> +
> +#define DP_TEST_V_START_HI 0x228
> +#define DP_TEST_V_START_LO 0x229
> +
> +#define DP_TEST_HSYNC_HI 0x22A
You should add bit definitions for this, as bit 7 is polarity, and only
bits 6:0 are the hsync high order bits.
> +#define DP_TEST_HSYNC_LO 0x22B
> +
> +#define DP_TEST_VSYNC_HI 0x22C
Same as DP_TEST_HSYNC_HI.
> +#define DP_TEST_VSYNC_LO 0x22D
> +
> +#define DP_TEST_H_WIDTH_HI 0x22E
> +#define DP_TESt_H_WIDTH_LO 0x22F
^ should be T
> +
> +#define DP_TEST_V_HEIGHT_HI 0x230
> +#define DP_TEST_V_HEIGHT_LO 0x231
> +
> +#define DP_TEST_MISC_LO 0x232
The other definitions have HI and LO because they contain a 15- or
16-bit value spread across two offsets. This is not the case here. I'd
call these DP_TEST_MISC0 and DP_TEST_MISC1.
> +# define DP_TEST_SYNC_CLOCK_MASK (1 << 0)
> +# define DP_CLOCK_ASYNC (0x0)
> +# define DP_CLOCK_SYNC (0x1)
Single-bit values should just be TEST_SYNCHRONOUS_CLOCK (1 << 0). No
masks, shifts or values.
> +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
> +# define DP_TEST_COLOR_FORMAT_SHIFT 1
> +# define DP_COLOR_FORMAT_RGB (0x0)
> +# define DP_COLOR_FORMAT_YCbCr422 (0x1)
> +# define DP_COLOR_FORMAT_YCbCr444 (0x2)
The values should be shifted to the right position,
e.g. DP_COLOR_FORMAT_RGB (0 << 1). The usage pattern would be:
if ((x & DP_TEST_COLOR_FORMAT_MASK) == DP_COLOR_FORMAT_RGB)
or
x &= ~DP_TEST_COLOR_FORMAT_MASK;
x |= DP_COLOR_FORMAT_YCbCr422;
> +# define DP_TEST_DYNAMIC_RANGE_MASK (1 << 3)
> +# define DP_TEST_DYNAMIC_RANGE_SHIFT 3
Single-bit values should just be DP_TEST_DYNAMIC_RANGE (1 << 3).
Same for all of the defines below.
BR,
Jani.
> +# define DP_VESA_RANGE (0x0)
> +# define DP_CEA_RANGE (0x1)
> +# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
> +# define DP_TEST_BIT_DEPTH_SHIFT 5
> +# define DP_TEST_BIT_DEPTH_6 (0x0)
> +# define DP_TEST_BIT_DEPTH_8 (0x1)
> +# define DP_TEST_BIT_DEPTH_10 (0x2)
> +# define DP_TEST_BIT_DEPTH_12 (0x3)
> +# define DP_TEST_BIT_DEPTH_16 (0x4)
> +#define DP_TEST_MISC_HI 0x233
> +# define DP_TEST_REFRESH_DENOMINATOR_MASK (1 << 0)
> +# define REFRESH_DENOMINATOR_1 (0x0)
> +# define REFRESH_DENOMINATOR_1_001 (0x1)
> +# define DP_TEST_INTERLACED_MASK (1 << 1)
> +# define DP_NON_INTERLACED (0x0)
> +# define DP_INTERLACED (0x1)
> +
> +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
>
> #define DP_TEST_CRC_R_CR 0x240
> #define DP_TEST_CRC_G_Y 0x242
--
Jani Nikula, Intel Open Source Technology Center
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