On Tue, Jan 10, 2017 at 06:17:42PM +0200, Joonas Lahtinen wrote:
> On ti, 2017-01-10 at 14:47 +0000, Chris Wilson wrote:
> > Start converting over from the byte count to its semantic macro, either
> > we want to allocate the size of a physical page in main memory or we
> > want the size of a virtual page in the GTT. 4096 could mean either, but
> > PAGE_SIZE and I915_GTT_PAGE_SIZE are explicit and should help improve
> > code comprehension and future changes. In the future, we may want to use
> > variable GTT page sizes and so have the challenge of knowing which
> > hardcoded values were used to represent a physical page vs the virtual
> > page.
> >
> > v2: Look for a few more 4096s to convert, discover IS_ALIGNED().
> > v3: 4096ul paranoia, make fence alignment a distinct value of 4096, keep
> > bdw stolen w/a as 4096 until we know better.
> > v4: Add asserts that i915_vma_insert() start/end are aligned to GTT page
> > sizes.
> >
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>
> <SNIP>
>
> > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> > @@ -47,5 +47,7 @@ struct drm_i915_fence_reg {
> > > bool dirty;
> > };
> >
> > +#define I965_FENCE_PAGE 4096UL
>
> I'm pretty sure I'd look for this from the very top of the file before
> structs. Any specific reason not there?
>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Bumped the macro and pushed. Even if this patch is not perfect, I think
it is a good step forward into sorting through the 4096.
Thanks,
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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