On Mon, Jan 09, 2017 at 04:19:03PM +0000, Tvrtko Ursulin wrote: > >diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > >index a5fe299da1d3..c6922a5f0514 100644 > >--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > >+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > >@@ -438,7 +438,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj, > > memset(&cache->node, 0, sizeof(cache->node)); > > ret = drm_mm_insert_node_in_range_generic > > (&ggtt->base.mm, &cache->node, > >- 4096, 0, I915_COLOR_UNEVICTABLE, > >+ PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE, > > This one is both really, hardcodes that they have to be equal. Hm, > yeah don't know. Still there is value in doing this patch so leave > the problem for later. Hmm, true. Such usage does pose interesting times ahead. We will probably need a MIN_GTT_PAGE_SIZE == PAGE_SIZE. > Replacing of 4096-es with names is welcomed, I am just not sure we > need two. Since it will be fixed to eternity perhaps we could just > have PAGE_SIZE for brevity. Not sure. Second opinions please! :) GTT_PAGE_SIZE may become variable, which is the fun. Not sure if MIN_ALIGNMENT will change with it or be implementation specific. This pass was more to do with splitting the actual PAGE_SIZE from our GTT units. There are still a few 4096s that I don't know the meaning behind. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
