On pe, 2017-01-06 at 15:25 +0000, Chris Wilson wrote: > Since the partial offset must be page aligned, we can use those low 12 > bits to encode the size of the partial view (which then cannot be larger > than 8MiB in pages). > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Lets just not, it makes the code unnecessarily hard to read (and for $DEITY's sake, I wrote the initial partial code). I think we have enough bugs in the MMIO parts that have to deal with packed registers. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
