On pe, 2017-01-06 at 15:25 +0000, Chris Wilson wrote:
> Ensure the view occupies the full tile row so that reads/writes into the
> VMA do not escape (via fenced detiling) into neighbouring objects - we
> will pad the object with scratch pages to satisfy the fence. This
> applies the lazy-tiling we employed on gen2/3 to gen4+.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
<SNIP>
> u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
> - u64 size, int tiling_mode)
> + u64 size, int tiling_mode, unsigned int stride)
> {
> u64 ggtt_size;
>
> - GEM_BUG_ON(size == 0);
> + GEM_BUG_ON(!size);
>
> - if (INTEL_GEN(dev_priv) >= 4 ||
> - tiling_mode == I915_TILING_NONE)
> + if (tiling_mode == I915_TILING_NONE)
> return size;
>
> + GEM_BUG_ON(!stride);
> +
> + if (INTEL_GEN(dev_priv) >= 4) {
> + stride *= tiling_mode == I915_TILING_Y ? 32 : 8;
(Split from tile_row_pages and) use tile_row_size() here? I915_TILING_Y
? 32 : 8 should really be in one place.
> + GEM_BUG_ON(stride & 4095);
~PAGE_MASK? Or even (4096 - 1) is better, so that it gets caught when
converting to non-hardcoded page sizes. CC'ing Matt.
> + return roundup(size, stride);
> + }
> +
> /* Previous chips need a power-of-two fence region when tiling */
> if (IS_GEN3(dev_priv))
> ggtt_size = 1024*1024;
Other than that,
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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