On Mon, Jan 09, 2017 at 10:24:01AM +0000, Chris Wilson wrote:
> On a non-llc system, the objects are created with .cache_level =
> CACHE_NONE and so the transition to uncached for scanout is a no-op.
> However, if the object was never written to, it will still be in the CPU
> domain (having been zeroed out by shmemfs). Those cachelines need to be
> flushed prior to display.
>
> Reported-by: Vito Caputo
> Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when pinning the scanout")
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: <drm-intel-fixes@xxxxxxxxxxxxxxxxxxxxx> # v4.10-rc1+
> ---
> drivers/gpu/drm/i915/i915_gem.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 76689b59fc90..e64d0ea6113d 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2327,6 +2327,7 @@ static void i915_sg_trim(struct sg_table *orig_st)
> if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN))
> return;
>
> + new_st->orig_nents = orig_st->orig_nents; /* XXX lies for
Oops. Ignore this chunk!
> new_sg = new_st.sgl;
> for_each_sg(orig_st->sgl, sg, orig_st->nents, i) {
> sg_set_page(new_sg, sg_page(sg), sg->length, 0);
> @@ -3514,7 +3515,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
>
> /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
> - if (obj->cache_dirty) {
> + if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
> i915_gem_clflush_object(obj, true);
> intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
> }
> --
> 2.11.0
>
--
Chris Wilson, Intel Open Source Technology Centre
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