On Fri, 2017-01-06 at 21:59 +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
>
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right
> after setup_vsc
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Jim Bride <jim.bride@xxxxxxxxxxxxxxx>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@xxxxxxxxx>
> Signed-off-by: Patil Deepti <deepti.patil@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 7 +++++++
> drivers/gpu/drm/i915/intel_psr.c | 9 ++++++++-
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP 3
> +#define CHICKEN_TRANS_BIT12 (1<<12)
> +#define CHICKEN_TRANS_BIT15 (1<<15)
> +
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE (1<<31)
> #define DISP_TILE_SURFACE_SWIZZLING (1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 7020f42..bcfe0db 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -348,7 +348,6 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
> val |= EDP_PSR2_TP2_TIME_100;
> else
> val |= EDP_PSR2_TP2_TIME_50;
> -
I'm afraid you missed this space here and removed one extra line.
> I915_WRITE(EDP_PSR2_CTL, val);
> }
>
> @@ -475,6 +474,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> + uint32_t chicken_trans = 0;
what about invert the order below so you don't need to initialize this
as 0 here.
chicken_trans = CHICKEN_TRANS_BIT12;
if (dev_priv->psr.y_cord_support)
chicken_trans |= CHICKEN_TRANS_BIT15;
>
> if (!HAS_PSR(dev_priv)) {
> DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +505,13 @@ void intel_psr_enable(struct intel_dp *intel_dp)
> dev_priv->psr.psr2_support = false;
> else
> skl_psr_setup_su_vsc(intel_dp);
> +
> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans = CHICKEN_TRANS_BIT15;
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
or at least use |= here...
> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
> } else {
> /* set up vsc header for psr1 */
> hsw_psr_setup_vsc(intel_dp);
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