On Mon, Jan 2, 2017 at 9:43 AM, Nagaraju, Vathsala <vathsala.nagaraju@xxxxxxxxx> wrote: > Hi Daniel, > > In the series ,this is the only patch which has changes in drm/drm_dp_helper.h, and just now, Jani put the reviewed-tag. > Should I post the series to dri-devel@xxxxxxxxxxxxxxxxxxxxx ? please advise. Yes. Context matters (and Jani can see the context since he's on intel-gfx, but not everyone on dri-devel is on both lists). -Daniel > Regards, > Vathsala > > -----Original Message----- > From: Daniel Vetter [mailto:daniel.vetter@xxxxxxxx] On Behalf Of Daniel Vetter > Sent: Monday, January 2, 2017 1:49 PM > To: Nagaraju, Vathsala <vathsala.nagaraju@xxxxxxxxx> > Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx; intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Patil, Deepti <deepti.patil@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx> > Subject: Re: [PATCH 01/10] drm : adds Y-coordinate and Colorimetry Format > > On Sat, Dec 31, 2016 at 07:48:38AM +0530, vathsala nagaraju wrote: >> PSR2 vsc revision number hb2( as per table 6-11)is updated to >> 4 or 5 based on Y cordinate and Colorimetry Format as below 04h = 3D >> stereo + PSR/PSR2 + Y-coordinate. >> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel >> Encoding/Colorimetry Format indication. A DP Source device is allowed >> to indicate the pixel encoding/colorimetry format to the DP Sink >> device with VSC SDP only when the DP Sink device supports it ( >> i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the >> DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3; is >> set to 1). >> >> v2: (Jani) >> - Change DP_PSR_Y_COORDINATE to DP_PSR2_SU_Y_COORDINATE_REQUIRED. >> - Add DP_PSR2_SU_GRANULARITY_REQUIRED. >> - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX. >> - Add GTC_CAP and AV_SYNC_CAP, other bits in DPRX_FEATURE_ENUMERATION_LIST. >> >> v3: (Jani) >> - Add support for bits 7:4 and 1 as per DP v1.4 for >> DPRX_FEATURE_ENUMERATION_LIST. >> >> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >> Cc: Jim Bride <jim.bride@xxxxxxxxxxxxxxx> >> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@xxxxxxxxx> >> Signed-off-by: Patil Deepti <deepti.patil@xxxxxxxxx> > > Please cc the entire patch series to all mailing lists, so that people have the full context. > > Thanks, Daniel > >> --- >> include/drm/drm_dp_helper.h | 13 ++++++++++++- >> 1 file changed, 12 insertions(+), 1 deletion(-) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index 55bbeb0..0468135 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -194,7 +194,8 @@ >> # define DP_PSR_SETUP_TIME_0 (6 << 1) >> # define DP_PSR_SETUP_TIME_MASK (7 << 1) >> # define DP_PSR_SETUP_TIME_SHIFT 1 >> - >> +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ >> +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ >> /* >> * 0x80-0x8f describe downstream port capabilities, but there are two layouts >> * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it >> was not, @@ -568,6 +569,16 @@ >> #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ >> # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) >> >> +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ >> +# define DP_GTC_CAP (1 << 0) /* DP 1.3 */ >> +# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ >> +# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ >> +# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ >> +# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ >> +# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ >> +# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ >> +# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ >> + >> /* DP 1.2 Sideband message defines */ >> /* peer device type - DP 1.2a Table 2-92 */ >> #define DP_PEER_DEVICE_NONE 0x0 >> -- >> 1.9.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
