On Mon, 2016-12-19 at 19:28 +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Move ilk_pipe_pixel_rate() next to its only caller
> (intel_crtc_compute_pixel_rate()).
Assuming a rebased patch 1,
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@xxxxxxxxx>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 33 ---------------------------------
> 3 files changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 409537011b28..5e18a598117c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6229,6 +6229,41 @@ static bool intel_crtc_supports_double_wide(const
> struct intel_crtc *crtc)
> (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
> }
>
> +static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
> *pipe_config)
> +{
> + uint32_t pixel_rate;
> +
> + pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
> +
> + /*
> + * We only use IF-ID interlacing. If we ever use
> + * PF-ID we'll need to adjust the pixel_rate here.
> + */
> +
> + if (pipe_config->pch_pfit.enabled) {
> + uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
> + uint32_t pfit_size = pipe_config->pch_pfit.size;
> +
> + pipe_w = pipe_config->pipe_src_w;
> + pipe_h = pipe_config->pipe_src_h;
> +
> + pfit_w = (pfit_size >> 16) & 0xFFFF;
> + pfit_h = pfit_size & 0xFFFF;
> + if (pipe_w < pfit_w)
> + pipe_w = pfit_w;
> + if (pipe_h < pfit_h)
> + pipe_h = pfit_h;
> +
> + if (WARN_ON(!pfit_w || !pfit_h))
> + return pixel_rate;
> +
> + pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
> + pfit_w * pfit_h);
> + }
> +
> + return pixel_rate;
> +}
> +
> static void intel_crtc_compute_pixel_rate(struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc-
> >dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 40074827f01d..4fd03b73d863 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1791,7 +1791,6 @@ bool skl_wm_level_equals(const struct skl_wm_level *l1,
> bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
> const struct skl_ddb_entry *ddb,
> int ignore);
> -uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
> bool ilk_disable_lp_wm(struct drm_device *dev);
> int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
> static inline int intel_enable_rc6(void)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fe522ec21502..cd81b51291d6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1701,39 +1701,6 @@ static void i845_update_wm(struct intel_crtc
> *unused_crtc)
> I915_WRITE(FW_BLC, fwater_lo);
> }
>
> -uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
> -{
> - uint32_t pixel_rate;
> -
> - pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
> -
> - /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
> - * adjust the pixel_rate here. */
> -
> - if (pipe_config->pch_pfit.enabled) {
> - uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
> - uint32_t pfit_size = pipe_config->pch_pfit.size;
> -
> - pipe_w = pipe_config->pipe_src_w;
> - pipe_h = pipe_config->pipe_src_h;
> -
> - pfit_w = (pfit_size >> 16) & 0xFFFF;
> - pfit_h = pfit_size & 0xFFFF;
> - if (pipe_w < pfit_w)
> - pipe_w = pfit_w;
> - if (pipe_h < pfit_h)
> - pipe_h = pfit_h;
> -
> - if (WARN_ON(!pfit_w || !pfit_h))
> - return pixel_rate;
> -
> - pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
> - pfit_w * pfit_h);
> - }
> -
> - return pixel_rate;
> -}
> -
> /* latency must be in 0.1us units. */
> static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t
> latency)
> {
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