From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> CCK houses various important clock related registers. Let's dump those as well. Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- tools/registers/cherryview | 1 + tools/registers/valleyview | 1 + tools/registers/vlv_cck.txt | 11 +++++++++++ 3 files changed, 13 insertions(+) create mode 100644 tools/registers/vlv_cck.txt diff --git a/tools/registers/cherryview b/tools/registers/cherryview index 9b94d026b584..47d79acf9c79 100644 --- a/tools/registers/cherryview +++ b/tools/registers/cherryview @@ -6,4 +6,5 @@ chv_display_base.txt chv_dpio_phy_x2.txt chv_dpio_phy_x1.txt vlv_dsi.txt +vlv_cck.txt gen7_other.txt diff --git a/tools/registers/valleyview b/tools/registers/valleyview index 2611a982a7ef..a4722f54f8eb 100644 --- a/tools/registers/valleyview +++ b/tools/registers/valleyview @@ -4,4 +4,5 @@ vlv_display_base.txt vlv_dpio_phy.txt vlv_dsi.txt vlv_flisdsi.txt +vlv_cck.txt gen7_other.txt diff --git a/tools/registers/vlv_cck.txt b/tools/registers/vlv_cck.txt new file mode 100644 index 000000000000..60bcdc7f17ba --- /dev/null +++ b/tools/registers/vlv_cck.txt @@ -0,0 +1,11 @@ +('CCK_FUSE_0', '0x08', 'CCK') +('CCK_DSI_PLL_FUSE', '0x44', 'CCK') +('CCK_DSI_PLL_CONTROL', '0x48', 'CCK') +('CCK_DSI_PLL_DIVIDER', '0x4c', 'CCK') +('CCK_CZ_CLOCK_CONTROL', '0x62', 'CCK') +('CCK_GPLL_CLOCK_CONTROL', '0x67', 'CCK') +('CCK_DISPLAY_CLOCK_CONTROL', '0x6b', 'CCK') +('CCK_DISPLAY_REF_CLOCK_CONTROL', '0x6c', 'CCK') +('CCK_MIPI_ESCAPE_CONTROL', '0x6d', 'CCK') +('CCK_DSI0_CONTROL', '0x6e', 'CCK') +('CCK_DSI1_CONTROL', '0x6f', 'CCK') -- 2.10.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx