On Thu, 15 Dec 2016, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Mon, Dec 12, 2016 at 02:57:44PM +0800, Wang Elaine wrote:
>> From: Elaine Wang <elaine.wang@xxxxxxxxx>
>>
>> Some platforms don't have display. To avoid accessing the
>> non-existent registers, check HAS_PCH_NOP before invoking
>> display IRQ install or reset function.
>>
>> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
>> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
>> Signed-off-by: Elaine Wang <elaine.wang@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_irq.c | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 0b119b9..369a038 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2990,8 +2990,10 @@ static void gen8_irq_reset(struct drm_device *dev)
>> POWER_DOMAIN_PIPE(pipe)))
>> GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
>>
>> - GEN5_IRQ_RESET(GEN8_DE_PORT_);
>> - GEN5_IRQ_RESET(GEN8_DE_MISC_);
>> + if (!HAS_PCH_NOP(dev_priv)) {
>> + GEN5_IRQ_RESET(GEN8_DE_PORT_);
>> + GEN5_IRQ_RESET(GEN8_DE_MISC_);
>> + }
>
> Hmm. These are north side registers so looking at PCH_NOP feels
> questionable.
Indeed, num_pipes == 0 isn't exactly the same thing as HAS_PCH_NOP.
Jani.
>
>> GEN5_IRQ_RESET(GEN8_PCU_);
>>
>> if (HAS_PCH_SPLIT(dev_priv))
>> @@ -3414,7 +3416,9 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>> ibx_irq_pre_postinstall(dev);
>>
>> gen8_gt_irq_postinstall(dev_priv);
>> - gen8_de_irq_postinstall(dev_priv);
>> +
>> + if (!HAS_PCH_NOP(dev_priv))
>> + gen8_de_irq_postinstall(dev_priv);
>>
>> if (HAS_PCH_SPLIT(dev_priv))
>> ibx_irq_postinstall(dev);
>> --
>> 1.9.1
--
Jani Nikula, Intel Open Source Technology Center
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