On 11/17/2016 3:06 PM, Tvrtko Ursulin wrote:
On 17/11/2016 09:28, Chris Wilson wrote:
On Thu, Nov 17, 2016 at 09:17:35AM +0000, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Commit ed4596ea992d ("drm/i915/guc: WA to address the Ringbuffer
coherency issue"), based on incorrect assumptions from a partialy
broken commit 0dd356bb6ff5 ("drm/i915: Eliminate Gen9 special
case") used POSTING_READ_FW instead of the POSTING_READ. With the
latter buggy commit fixed this call site needs fixing as well.
The theory here is that we don't need the powerwell to force the write
from CPU to be visible before another agent.
I missed the report, so I am genuinely interested in knowing whether the
theory about the write being posted without the powerwll.
Just that the commit message for the patch used "guc registers are not
in any forcewake domain" reasoning, which was false - based on a
partially broken patch. See "drm/i915: Fix gen9 forcewake range table".
Regards,
Tvrtko
Verified this fix without forcewake, so this patch will not be needed.
Have couple of queries. Chris, could you please clarify:
1. why POSTING_READ is done in flush_gtt_write_domain and not
POSTING_READ_FW like this case?
2. how does read from forcewake mmio range work if well is down?
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
