On Fri, Nov 25, 2016 at 04:41:14PM +0200, Abdiel Janulgue wrote:
> A lot of igt testcases need some GPU workload to make sure a race
> window is big enough. Unfortunately having a fixed amount of
> workload leads to spurious test failures or overly long runtimes
> on some fast/slow platforms. This library contains functionality
> to submit GPU workloads that should consume exactly a specific
> amount of time.
>
> v10: Split timeout function. Clarify function names (Chris)
> v11: From Chris:
> * Add gem_quiescent_gpu exit handler
> * Use gem_bo_busy
> * Skip spin->handle > 0 checks
> * Ensure terminate batch on free
> * Remove igt_spin_batch_wait
> * Remove single-ring limitation
> v12: Hook into gem_quiescent_gpu exit handler to idle the GPU if
> the user terminates tests with ^C
> v13: Use the kernel's list to handle spinner objects
> v14: Use multiple signals, cycle available signals from
> SIGRTMIN to SIGRTMAX. Reuse list definition from Chamelium
> patches.
>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: tomeu@xxxxxxxxxxxxxxx
> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@xxxxxxxxxxxxx>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@xxxxxxxxxxxxxxx>
> ---
> .../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
> lib/Makefile.sources | 2 +
> lib/drmtest.c | 3 +
> lib/igt.h | 1 +
> lib/igt_dummyload.c | 300 +++++++++++++++++++++
> lib/igt_dummyload.h | 49 ++++
> 6 files changed, 356 insertions(+)
> create mode 100644 lib/igt_dummyload.c
> create mode 100644 lib/igt_dummyload.h
>
> diff --git a/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml b/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
> index c862f2a..55902ab 100644
> --- a/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
> +++ b/docs/reference/intel-gpu-tools/intel-gpu-tools-docs.xml
> @@ -32,6 +32,7 @@
> <xi:include href="xml/intel_io.xml"/>
> <xi:include href="xml/igt_vc4.xml"/>
> <xi:include href="xml/igt_vgem.xml"/>
> + <xi:include href="xml/igt_dummyload.xml"/>
> </chapter>
> <xi:include href="xml/igt_test_programs.xml"/>
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index e8e277b..7fc5ec2 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -75,6 +75,8 @@ lib_source_list = \
> igt_draw.h \
> igt_pm.c \
> igt_pm.h \
> + igt_dummyload.c \
> + igt_dummyload.h \
> uwildmat/uwildmat.h \
> uwildmat/uwildmat.c \
> $(NULL)
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 44abc7e..be1dc93 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -57,6 +57,7 @@
> #include "config.h"
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
> +#include "igt_dummyload.h"
>
> /**
> * SECTION:drmtest
> @@ -159,6 +160,8 @@ void gem_quiescent_gpu(int fd)
> struct drm_i915_gem_exec_object2 obj;
> unsigned ring;
>
> + igt_terminate_spin_batches();
> +
> memset(&obj, 0, sizeof(obj));
> obj.handle = gem_create(fd, 4096);
> gem_write(fd, obj.handle, 0, &bbe, sizeof(&bbe));
> diff --git a/lib/igt.h b/lib/igt.h
> index d751f24..a0028d5 100644
> --- a/lib/igt.h
> +++ b/lib/igt.h
> @@ -32,6 +32,7 @@
> #include "igt_core.h"
> #include "igt_debugfs.h"
> #include "igt_draw.h"
> +#include "igt_dummyload.h"
> #include "igt_fb.h"
> #include "igt_gt.h"
> #include "igt_kms.h"
> diff --git a/lib/igt_dummyload.c b/lib/igt_dummyload.c
> new file mode 100644
> index 0000000..d388f6e
> --- /dev/null
> +++ b/lib/igt_dummyload.c
> @@ -0,0 +1,300 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "igt.h"
> +#include "igt_dummyload.h"
> +#include <time.h>
> +#include <signal.h>
> +#include <sys/syscall.h>
> +
> +/**
> + * SECTION:igt_dummyload
> + * @short_description: Library for submitting GPU workloads
> + * @title: Dummyload
> + * @include: igt.h
> + *
> + * A lot of igt testcases need some GPU workload to make sure a race window is
> + * big enough. Unfortunately having a fixed amount of workload leads to
> + * spurious test failures or overly long runtimes on some fast/slow platforms.
> + * This library contains functionality to submit GPU workloads that should
> + * consume exactly a specific amount of time.
> + */
> +
> +#define LOCAL_I915_EXEC_BSD_SHIFT (13)
> +#define LOCAL_I915_EXEC_BSD_MASK (3 << LOCAL_I915_EXEC_BSD_SHIFT)
> +
> +#define ENGINE_MASK (I915_EXEC_RING_MASK | LOCAL_I915_EXEC_BSD_MASK)
> +
> +static const int bo_size = 4096;
> +static struct igt_list spin_list = { &(spin_list), &(spin_list) };
> +static int spin_object_timer_id = 0;
> +
> +static void
> +fill_object(struct drm_i915_gem_exec_object2 *obj, uint32_t gem_handle,
> + struct drm_i915_gem_relocation_entry *relocs, uint32_t count)
> +{
> + memset(obj, 0, sizeof(*obj));
> + obj->handle = gem_handle;
> + obj->relocation_count = count;
> + obj->relocs_ptr = (uintptr_t)relocs;
> +}
> +
> +static void
> +fill_reloc(struct drm_i915_gem_relocation_entry *reloc,
> + uint32_t gem_handle, uint32_t offset,
> + uint32_t read_domains, uint32_t write_domains)
> +{
> + reloc->target_handle = gem_handle;
> + reloc->delta = 0;
> + reloc->offset = offset * sizeof(uint32_t);
> + reloc->presumed_offset = 0;
> + reloc->read_domains = read_domains;
> + reloc->write_domain = write_domains;
> +}
> +
> +/*
> + * Needs to be global. Signal handlers don't accept arguments
> + */
> +static uint32_t *batch;
> +
> +static uint32_t emit_recursive_batch(int fd, int engine,
> + unsigned int dep_handle)
> +{
> + const int gen = intel_gen(intel_get_drm_devid(fd));
> + struct drm_i915_gem_exec_object2 obj[2];
> + struct drm_i915_gem_relocation_entry relocs[2];
> + struct drm_i915_gem_execbuffer2 execbuf;
> + unsigned int engines[16];
> + unsigned int nengine, handle;
> + int i = 0, reloc_count = 0, buf_count = 0;
> +
> + buf_count = 0;
> + nengine = 0;
> + if (engine < 0) {
> + for_each_engine(fd, engine)
> + if (engine)
> + engines[nengine++] = engine;
> + } else {
> + gem_require_ring(fd, engine);
> + engines[nengine++] = engine;
> + }
> + igt_require(nengine);
> +
> + memset(&execbuf, 0, sizeof(execbuf));
> + memset(obj, 0, sizeof(obj));
> + memset(relocs, 0, sizeof(relocs));
> +
> + execbuf.buffers_ptr = (uintptr_t) obj;
> + handle = gem_create(fd, bo_size);
> + batch = gem_mmap__gtt(fd, handle, bo_size, PROT_WRITE);
> + igt_assert(batch);
> + gem_set_domain(fd, handle,
> + I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
> +
> + if (dep_handle > 0) {
> + /* dummy write to dependency */
> + fill_object(&obj[buf_count], dep_handle, NULL, 0);
> + buf_count++;
> +
> + fill_reloc(&relocs[reloc_count], dep_handle, 256,
> + I915_GEM_DOMAIN_RENDER,
> + I915_GEM_DOMAIN_RENDER);
> + reloc_count++;
> + }
> +
> + if (gen >= 8) {
> + batch[i++] = MI_BATCH_BUFFER_START | 1 << 8 | 1;
> + /* recurse */
> + fill_reloc(&relocs[reloc_count], handle, i,
> + I915_GEM_DOMAIN_COMMAND, 0);
> + batch[i++] = 0;
> + batch[i++] = 0;
> + } else if (gen >= 6) {
> + batch[i++] = MI_BATCH_BUFFER_START | 1 << 8;
> + /* recurse */
> + fill_reloc(&relocs[reloc_count], handle, i,
> + I915_GEM_DOMAIN_COMMAND, 0);
> + batch[i++] = 0;
> + } else {
> + batch[i++] = MI_BATCH_BUFFER_START | 2 << 6 |
> + ((gen < 4) ? 1 : 0);
> + /* recurse */
> + fill_reloc(&relocs[reloc_count], handle, i,
> + I915_GEM_DOMAIN_COMMAND, 0);
> + batch[i++] = 0;
> + if (gen < 4)
> + relocs[reloc_count].delta = 1;
> + }
> + reloc_count++;
> +
> + fill_object(&obj[buf_count], handle, relocs, reloc_count);
> + buf_count++;
> +
> + for (i = 0; i < nengine; i++) {
> + execbuf.flags = engines[i];
> + execbuf.flags &= ~ENGINE_MASK;
> + execbuf.buffer_count = buf_count;
> + gem_execbuf(fd, &execbuf);
> + }
> +
> + return handle;
> +}
> +
> +static void exit_batch_handler(int sig, siginfo_t *info, void *spin)
> +{
> + struct sigaction act;
> +
> + *batch = MI_BATCH_BUFFER_END;
But we now have multiple signals, shouldn't you walk the list of active
spinners to see which matches this sig?
And then we can rid ourselves of the global batch, which is then moved
to spinner.
> + __sync_synchronize();
> +
> + memset(&act, 0, sizeof(act));
> + act.sa_handler = SIG_DFL;
> + igt_assert(sigaction(info->si_signo, &act, NULL) == 0);
> +}
> +void igt_spin_batch_set_timeout(igt_spin_t *spin, int64_t ns)
> +{
> + timer_t timer;
> + struct sigevent sev;
> + struct sigaction act, oldact;
> + struct itimerspec its;
> + int signum;
> +
> + igt_assert(ns > 0);
> + if (!spin)
> + return;
> +
> + if (spin_object_timer_id > SIGRTMAX - 1)
> + spin_object_timer_id = 0;
> + signum = SIGRTMIN + spin_object_timer_id++;
Ah, so we need to keep SIGRTMIN clear for the interruptible helper, and
really that should be SIGRTMIN+1 as valgrind wants SIGRTMIN for itself.
Anyway this needs to be a preincrement and a check for
static int spin_signo = SIGRTMIN;
if (spin_signo == SIGRTMAX)
spin_signo = SIGRTMIN;
spin->signo = ++spin_signo;
> +
> + memset(&sev, 0, sizeof(sev));
> + sev.sigev_notify = SIGEV_SIGNAL | SIGEV_THREAD_ID;
> + sev.sigev_notify_thread_id = gettid();
> + sev.sigev_signo = signum;
sev.sigev_signo = spin->signo;
--
Chris Wilson, Intel Open Source Technology Centre
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