On Thu, Nov 24, 2016 at 05:32:58PM +0200, Imre Deak wrote:
> The spec calls for the upper data byte to be cleared before most of the
> PCODE write commands, for others like IPS control it doesn't say
> anything about this byte. Let's clear it in case it's clobbered somehow,
> especially that there are places where we only do a PCODE write without
> a preceeding PCODE read.
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 29b6653..66c62f3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7838,6 +7838,7 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
> }
>
> I915_WRITE_FW(GEN6_PCODE_DATA, val);
> + I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
> I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
Hmm. Somehow we missed it in dddab346d828 ("drm/i915: Clear PCODE_DATA1 on SNB+")
even though my ramblings (which were quoted in the commit msg) stated that we
should do it in both the read and write functions.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> if (intel_wait_for_register_fw(dev_priv,
> --
> 2.5.0
--
Ville Syrjälä
Intel OTC
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