On Fri, Nov 04, 2016 at 11:08:38AM +0000, Chris Wilson wrote: > Valleyview and Cherryview are definitely limited to only scanning out > from the first 256MiB and 512MiB of the Global GTT respectively. Actually no. My VLVs (B3 and C0 steppings should that matter) would appear to be good up to 512MiB. The access just wrap every 512MiB, so I presume it just ignores the 3 msbs. My CHV seemed good all the way up to 4 GiB. When I tried the same test on an ELK I got some strange results. On the first run it seemed to handle things up to 512MiB or maybe even past it, but then once my test went back to lower addresses something fishy happened and I started to see failures. I need to figure out if my test is just buggy on ELK or if the hw gets semi-permanently confused when you feed it large addresses. > presume that this behaviour was inherited from the display block copied > from g4x (not Ironlake) and all earlier generations are similarly > affected. For simplicity, impose that these platforms must scanout from > the mappable region. > > Reported-by: Luis Botello <luis.botello.ortega@xxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98036 > Fixes: 2efb813d5388 ("drm/i915: Fallback to using unmappable memory for scanout") > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Akash Goel <akash.goel@xxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Cc: <drm-intel-fixes@xxxxxxxxxxxxxxxxxxxxx> # v4.9-rc1+ > --- > This leaves Ironlake -> Haswell with a bit of uncertainity. It is also > not clear if the scanout accessible region is similarly limited on all > gen8+, and so whether we need to similarly curtain the upper range for > their scanouts. > --- > drivers/gpu/drm/i915/i915_gem.c | 18 ++++++++++++++++-- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 269e2487c104..408875fbec66 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -3661,8 +3661,22 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, > if (view->type == I915_GGTT_VIEW_NORMAL) > vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, > PIN_MAPPABLE | PIN_NONBLOCK); > - if (IS_ERR(vma)) > - vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, 0); > + if (IS_ERR(vma)) { > + struct drm_i915_private *i915 = to_i915(obj->base.dev); > + unsigned int flags; > + > + /* Valleyview and Cherryview are definitely limited to scanning > + * out the first 256MiB and 512MiB respectively. Lets presume > + * this behaviour was inherited from their g4x display engine > + * and that all earlier gen are similarly limited. > + */ > + flags = 0; > + if (INTEL_GEN(i915) < 5 || > + IS_VALLEYVIEW(i915) || > + IS_CHERRYVIEW(i915)) > + flags = PIN_MAPPABLE; > + vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); > + } > if (IS_ERR(vma)) > goto err_unpin_display; > > -- > 2.10.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
