Since gen9 timestamp can be read from BLT ring (TIMESTAMP_BCSUNIT).
Add this register to reg_read ioctl whitelist.
cc=chris@xxxxxxxxxxxxxxxxxx
cc=arkadiusz.hiler@xxxxxxxxx
cc=michal.winiarski@xxxxxxxxx
Signed-off-by: Andrzej Lawrynowicz <andrzej.lawrynowicz@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e2b188d..c2c3fe6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1354,6 +1354,9 @@ static const struct register_whitelist {
{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
.size = 8, .gen_bitmask = GEN_RANGE(4, 9) },
+ { .offset_ldw = RING_TIMESTAMP(BLT_RING_BASE),
+ .offset_udw = RING_TIMESTAMP_UDW(BLT_RING_BASE),
+ .size = 8, .gen_bitmask = GEN_RANGE(9, 9) },
};
int i915_reg_read_ioctl(struct drm_device *dev,
--
2.10.1
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