On Wed, Oct 26, 2016 at 11:22:00AM -0700, Rodrigo Vivi wrote: > Since Broxton has same FBC block as BDW+ let's assume it also > don't have access to the stolen usable range. > > FBC is currently not saving power on Broxton and I believe > the compression threshold is limited to 1x. > > Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > Cc: Marc Herbert <marc.herbert@xxxxxxxxx> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_fbc.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index cbe2ebd..640db67 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -530,12 +530,11 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, > int ret; > u64 end; > > - /* The FBC hardware for BDW/SKL doesn't have access to the stolen > + /* The FBC hardware for gen8+ doesn't have access to the stolen > * reserved range size, so it always assumes the maximum (8mb) is used. Might I suggest correcting the comment to say megabyte instead of millibit while at it? > * If we enable FBC using a CFB on that memory range we'll get FIFO > * underruns, even if that range is not reserved by the BIOS. */ > - if (IS_BROADWELL(dev_priv) || > - IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) > + if (INTEL_INFO(dev_priv)->gen <= 8) INTEL_GEN(dev_priv) Also, shouldn't this be >= 8? Also, remember that gen8 also includes CherryView -- is the behaviour the same there? > end = ggtt->stolen_size - 8 * 1024 * 1024; > else > end = ggtt->stolen_usable_size; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
