On Tue, 2016-10-25 at 11:46 +0300, Ville Syrjälä wrote:
> On Mon, Oct 24, 2016 at 09:18:37PM -0700, Dhinakaran Pandiyan wrote:
> > According to BSpec, cdclk has to be not less than 432 MHz with DP audio
> > enabled, port width x4, and link rate HBR2 (5.4 GHz)
> >
> > Having a lower cdclk triggers pipe underruns, which then lead to displays
> > continuously cycling off and on. This is essential for DP MST audio as the
> > link is trained at HBR2 and 4 lanes by default.
> >
> > v2: Restrict fix to BDW
> > Retain the set cdclk across modesets (Ville)
> >
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++++++++++++++---
> > 1 file changed, 25 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index a94f7d1..8c59651 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10260,6 +10260,18 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> > bxt_set_cdclk(to_i915(dev), req_cdclk);
> > }
> >
> > +static unsigned int bdw_dp_audio_cdclk(struct intel_crtc_state *crtc_state)
> > +{
> > +
>
> Useless blank line.
>
> > + if (intel_crtc_has_dp_encoder(crtc_state) &&
> > + crtc_state->has_audio &&
> > + crtc_state->port_clock >= 540000 &&
> > + crtc_state->lane_count == 4)
> > + return 432000;
> > +
> > + return 0;
> > +}
> > +
> > /* compute the max rate for new configuration */
> > static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> > {
> > @@ -10275,7 +10287,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> > sizeof(intel_state->min_pixclk));
> >
> > for_each_crtc_in_state(state, crtc, cstate, i) {
> > - int pixel_rate;
> > + unsigned int pixel_rate;
> >
> > crtc_state = to_intel_crtc_state(cstate);
> > if (!crtc_state->base.enable) {
> > @@ -10285,9 +10297,19 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
> >
> > pixel_rate = ilk_pipe_pixel_rate(crtc_state);
> >
> > + if (IS_BROADWELL(dev_priv)) {
> > /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> > - if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
> > - pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> > + if (crtc_state->ips_enabled)
> > + pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
> > +
> > + /* BSpec says "Do not use DisplayPort with CDCLK less than
> > + * 432 MHz, audio enabled, port width x4, and link rate
> > + * HBR2 (5.4 GHz), or else there may be audio corruption or
> > + * screen corruption."
> > + */
>
> Indentation of the comments is wrong.
>
> > + pixel_rate = max(pixel_rate,
> > + bdw_dp_audio_cdclk(crtc_state));
> > + }
> >
> > intel_state->min_pixclk[i] = pixel_rate;
>
> Otherwise I suppose this ought to work.
>
> So with the formatting stuff fixed this is
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The whole min_pixclk vs. pixel_rate vs. cdclk thing is a bit of a mess
> though. So it could use a thorough cleaning to make it less confusing.
> I'm tinking we might just want to start tracking a minimum acceptable
> cdclk per pipe. Probably the main thing would be to pull in the
> 5%/10% guardband handling here for all platforms.
>
Yeah, definitely needs some work. As you wrote in the previous review,
we can get rid of tracking min_pixclk and track min_cdclk instead. I
could not find any other use for min_pixclk other than computing cdclk.
Thanks for the review.
-DK
> > }
> > --
> > 2.7.4
>
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