On Tue, Oct 04, 2016 at 03:32:13PM +0300, Ander Conselvan de Oliveira wrote:
> Struct intel_shared_dpll_config is used to hold the state of the DPLL in
> the "atomic" sense, so call it state like everything else atomic.
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 12 +++----
> drivers/gpu/drm/i915/intel_atomic.c | 6 ++--
> drivers/gpu/drm/i915/intel_ddi.c | 10 +++---
> drivers/gpu/drm/i915/intel_display.c | 22 ++++++------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 68 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_dpll_mgr.h | 4 +--
> drivers/gpu/drm/i915/intel_drv.h | 4 +--
> 7 files changed, 63 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index da71413..12b97af 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3229,14 +3229,14 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>
> seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
> seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
> - pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
> + pll->state.crtc_mask, pll->active_mask, yesno(pll->on));
> seq_printf(m, " tracked hardware state:\n");
> - seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
> + seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll);
> seq_printf(m, " dpll_md: 0x%08x\n",
> - pll->config.hw_state.dpll_md);
> - seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
> - seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
> - seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
> + pll->state.hw_state.dpll_md);
> + seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
> + seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
> + seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);
> }
> drm_modeset_unlock_all(dev);
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index c5a1667..fa6dc43 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -267,7 +267,7 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
>
> static void
> intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
> - struct intel_shared_dpll_config *shared_dpll)
> + struct intel_shared_dpll_state *shared_dpll)
> {
> enum intel_dpll_id i;
>
> @@ -275,11 +275,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
> for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
>
> - shared_dpll[i] = pll->config;
> + shared_dpll[i] = pll->state;
> }
> }
>
> -struct intel_shared_dpll_config *
> +struct intel_shared_dpll_state *
> intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
> {
> struct intel_atomic_state *state = to_intel_atomic_state(s);
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 35f0b7c..4077205 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -992,7 +992,7 @@ static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
> return 0;
>
> pll = &dev_priv->shared_dplls[dpll];
> - state = &pll->config.hw_state;
> + state = &pll->state.hw_state;
>
> clock.m1 = 2;
> clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
> @@ -2401,7 +2401,7 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct intel_shared_dpll *pll = NULL;
> - struct intel_shared_dpll_config tmp_pll_config;
> + struct intel_shared_dpll_state tmp_pll_state;
> enum intel_dpll_id dpll_id;
>
> if (IS_BROXTON(dev_priv)) {
> @@ -2417,11 +2417,11 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
> pll->active_mask);
> return NULL;
> }
> - tmp_pll_config = pll->config;
> + tmp_pll_state = pll->state;
> if (!bxt_ddi_dp_set_dpll_hw_state(clock,
> - &pll->config.hw_state)) {
> + &pll->state.hw_state)) {
> DRM_ERROR("Could not setup DPLL\n");
> - pll->config = tmp_pll_config;
> + pll->state = tmp_pll_state;
> return NULL;
> }
> } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8bfde0..e6fe85b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13639,9 +13639,9 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
> }
>
> if (!crtc) {
> - I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
> + I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
> "more active pll users than references: %x vs %x\n",
> - pll->active_mask, pll->config.crtc_mask);
> + pll->active_mask, pll->state.crtc_mask);
>
> return;
> }
> @@ -13657,11 +13657,11 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv,
> "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
> pipe_name(drm_crtc_index(crtc)), pll->active_mask);
>
> - I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
> + I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
> "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
> - crtc_mask, pll->config.crtc_mask);
> + crtc_mask, pll->state.crtc_mask);
>
> - I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
> + I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
> &dpll_hw_state,
> sizeof(dpll_hw_state)),
> "pll hw state mismatch\n");
> @@ -13687,7 +13687,7 @@ verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
> I915_STATE_WARN(pll->active_mask & crtc_mask,
> "pll active mismatch (didn't expect pipe %c in active mask)\n",
> pipe_name(drm_crtc_index(crtc)));
> - I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
> + I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
> "pll enabled crtcs mismatch (found %x in enabled mask)\n",
> pipe_name(drm_crtc_index(crtc)));
> }
> @@ -16759,16 +16759,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
>
> pll->on = pll->funcs.get_hw_state(dev_priv, pll,
> - &pll->config.hw_state);
> - pll->config.crtc_mask = 0;
> + &pll->state.hw_state);
> + pll->state.crtc_mask = 0;
> for_each_intel_crtc(dev, crtc) {
> if (crtc->active && crtc->config->shared_dpll == pll)
> - pll->config.crtc_mask |= 1 << crtc->pipe;
> + pll->state.crtc_mask |= 1 << crtc->pipe;
> }
> - pll->active_mask = pll->config.crtc_mask;
> + pll->active_mask = pll->state.crtc_mask;
>
> DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
> - pll->name, pll->config.crtc_mask, pll->on);
> + pll->name, pll->state.crtc_mask, pll->on);
> }
>
> for_each_intel_encoder(dev, encoder) {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 15bf462..c88fc07 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -38,11 +38,11 @@ skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
> pll = &dev_priv->shared_dplls[i];
>
> /* Only want to check enabled timings first */
> - if (pll->config.crtc_mask == 0)
> + if (pll->state.crtc_mask == 0)
> continue;
>
> - if (memcmp(&dpll_hw_state, &pll->config.hw_state,
> - sizeof(pll->config.hw_state)) == 0) {
> + if (memcmp(&dpll_hw_state, &pll->state.hw_state,
> + sizeof(pll->state.hw_state)) == 0) {
> found = true;
> break;
> }
> @@ -52,8 +52,8 @@ skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
> for (i = DPLL_ID_SKL_DPLL1;
> ((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) {
> pll = &dev_priv->shared_dplls[i];
> - if (pll->config.crtc_mask == 0) {
> - pll->config.hw_state = dpll_hw_state;
> + if (pll->state.crtc_mask == 0) {
> + pll->state.hw_state = dpll_hw_state;
> break;
> }
> }
> @@ -106,7 +106,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> return;
>
> mutex_lock(&dev_priv->dpll_lock);
> - WARN_ON(!pll->config.crtc_mask);
> + WARN_ON(!pll->state.crtc_mask);
> if (!pll->active_mask) {
> DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
> WARN_ON(pll->on);
> @@ -139,7 +139,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
> mutex_lock(&dev_priv->dpll_lock);
> old_mask = pll->active_mask;
>
> - if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
> + if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) ||
> WARN_ON(pll->active_mask & crtc_mask))
> goto out;
>
> @@ -209,7 +209,7 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_shared_dpll *pll;
> - struct intel_shared_dpll_config *shared_dpll;
> + struct intel_shared_dpll_state *shared_dpll;
> enum intel_dpll_id i;
>
> shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
> @@ -249,7 +249,7 @@ static void
> intel_reference_shared_dpll(struct intel_shared_dpll *pll,
> struct intel_crtc_state *crtc_state)
> {
> - struct intel_shared_dpll_config *shared_dpll;
> + struct intel_shared_dpll_state *shared_dpll;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> enum intel_dpll_id i = pll->id;
>
> @@ -269,7 +269,7 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll,
> void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->dev);
> - struct intel_shared_dpll_config *shared_dpll;
> + struct intel_shared_dpll_state *shared_dpll;
> struct intel_shared_dpll *pll;
> enum intel_dpll_id i;
>
> @@ -279,7 +279,7 @@ void intel_shared_dpll_swap_state(struct drm_atomic_state *state)
> shared_dpll = to_intel_atomic_state(state)->shared_dpll;
> for (i = 0; i < dev_priv->num_shared_dpll; i++) {
> pll = &dev_priv->shared_dplls[i];
> - pll->config = shared_dpll[i];
> + pll->state = shared_dpll[i];
> }
> }
>
> @@ -305,8 +305,8 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
> static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
> - I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
> + I915_WRITE(PCH_FP0(pll->id), pll->state.hw_state.fp0);
> + I915_WRITE(PCH_FP1(pll->id), pll->state.hw_state.fp1);
> }
>
> static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
> @@ -328,7 +328,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
> /* PCH refclock must be enabled first */
> ibx_assert_pch_refclk_enabled(dev_priv);
>
> - I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
> + I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
>
> /* Wait for the clocks to stabilize. */
> POSTING_READ(PCH_DPLL(pll->id));
> @@ -339,7 +339,7 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
> *
> * So write it again.
> */
> - I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
> + I915_WRITE(PCH_DPLL(pll->id), pll->state.hw_state.dpll);
> POSTING_READ(PCH_DPLL(pll->id));
> udelay(200);
> }
> @@ -401,7 +401,7 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
> static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
> + I915_WRITE(WRPLL_CTL(pll->id), pll->state.hw_state.wrpll);
> POSTING_READ(WRPLL_CTL(pll->id));
> udelay(20);
> }
> @@ -409,7 +409,7 @@ static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
> static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
> struct intel_shared_dpll *pll)
> {
> - I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
> + I915_WRITE(SPLL_CTL, pll->state.hw_state.spll);
> POSTING_READ(SPLL_CTL);
> udelay(20);
> }
> @@ -852,7 +852,7 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
>
> val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
> DPLL_CTRL1_LINK_RATE_MASK(pll->id));
> - val |= pll->config.hw_state.ctrl1 << (pll->id * 6);
> + val |= pll->state.hw_state.ctrl1 << (pll->id * 6);
>
> I915_WRITE(DPLL_CTRL1, val);
> POSTING_READ(DPLL_CTRL1);
> @@ -865,8 +865,8 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
>
> skl_ddi_pll_write_ctrl1(dev_priv, pll);
>
> - I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
> - I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
> + I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1);
> + I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);
> POSTING_READ(regs[pll->id].cfgcr1);
> POSTING_READ(regs[pll->id].cfgcr2);
>
> @@ -1363,31 +1363,31 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> /* Write P1 & P2 */
> temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
> temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
> - temp |= pll->config.hw_state.ebb0;
> + temp |= pll->state.hw_state.ebb0;
> I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
>
> /* Write M2 integer */
> temp = I915_READ(BXT_PORT_PLL(port, 0));
> temp &= ~PORT_PLL_M2_MASK;
> - temp |= pll->config.hw_state.pll0;
> + temp |= pll->state.hw_state.pll0;
> I915_WRITE(BXT_PORT_PLL(port, 0), temp);
>
> /* Write N */
> temp = I915_READ(BXT_PORT_PLL(port, 1));
> temp &= ~PORT_PLL_N_MASK;
> - temp |= pll->config.hw_state.pll1;
> + temp |= pll->state.hw_state.pll1;
> I915_WRITE(BXT_PORT_PLL(port, 1), temp);
>
> /* Write M2 fraction */
> temp = I915_READ(BXT_PORT_PLL(port, 2));
> temp &= ~PORT_PLL_M2_FRAC_MASK;
> - temp |= pll->config.hw_state.pll2;
> + temp |= pll->state.hw_state.pll2;
> I915_WRITE(BXT_PORT_PLL(port, 2), temp);
>
> /* Write M2 fraction enable */
> temp = I915_READ(BXT_PORT_PLL(port, 3));
> temp &= ~PORT_PLL_M2_FRAC_ENABLE;
> - temp |= pll->config.hw_state.pll3;
> + temp |= pll->state.hw_state.pll3;
> I915_WRITE(BXT_PORT_PLL(port, 3), temp);
>
> /* Write coeff */
> @@ -1395,24 +1395,24 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp &= ~PORT_PLL_PROP_COEFF_MASK;
> temp &= ~PORT_PLL_INT_COEFF_MASK;
> temp &= ~PORT_PLL_GAIN_CTL_MASK;
> - temp |= pll->config.hw_state.pll6;
> + temp |= pll->state.hw_state.pll6;
> I915_WRITE(BXT_PORT_PLL(port, 6), temp);
>
> /* Write calibration val */
> temp = I915_READ(BXT_PORT_PLL(port, 8));
> temp &= ~PORT_PLL_TARGET_CNT_MASK;
> - temp |= pll->config.hw_state.pll8;
> + temp |= pll->state.hw_state.pll8;
> I915_WRITE(BXT_PORT_PLL(port, 8), temp);
>
> temp = I915_READ(BXT_PORT_PLL(port, 9));
> temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
> - temp |= pll->config.hw_state.pll9;
> + temp |= pll->state.hw_state.pll9;
> I915_WRITE(BXT_PORT_PLL(port, 9), temp);
>
> temp = I915_READ(BXT_PORT_PLL(port, 10));
> temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
> temp &= ~PORT_PLL_DCO_AMP_MASK;
> - temp |= pll->config.hw_state.pll10;
> + temp |= pll->state.hw_state.pll10;
> I915_WRITE(BXT_PORT_PLL(port, 10), temp);
>
> /* Recalibrate with new settings */
> @@ -1420,7 +1420,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp |= PORT_PLL_RECALIBRATE;
> I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
> temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> - temp |= pll->config.hw_state.ebb4;
> + temp |= pll->state.hw_state.ebb4;
> I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
>
> /* Enable PLL */
> @@ -1440,7 +1440,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
> temp &= ~LANE_STAGGER_MASK;
> temp &= ~LANESTAGGER_STRAP_OVRD;
> - temp |= pll->config.hw_state.pcsdw12;
> + temp |= pll->state.hw_state.pcsdw12;
> I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
> }
>
> @@ -1890,8 +1890,8 @@ void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
> struct intel_crtc *crtc,
> struct drm_atomic_state *state)
> {
> - struct intel_shared_dpll_config *shared_dpll_config;
> + struct intel_shared_dpll_state *shared_dpll_state;
>
> - shared_dpll_config = intel_atomic_get_shared_dpll_state(state);
> - shared_dpll_config[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
> + shared_dpll_state = intel_atomic_get_shared_dpll_state(state);
> + shared_dpll_state[dpll->id].crtc_mask &= ~(1 << crtc->pipe);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 06d61c5..6e3a0f1 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -93,7 +93,7 @@ struct intel_dpll_hw_state {
> pcsdw12;
> };
>
> -struct intel_shared_dpll_config {
> +struct intel_shared_dpll_state {
> unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
> struct intel_dpll_hw_state hw_state;
> };
> @@ -113,7 +113,7 @@ struct intel_shared_dpll_funcs {
> };
>
> struct intel_shared_dpll {
> - struct intel_shared_dpll_config config;
> + struct intel_shared_dpll_state state;
>
> unsigned active_mask; /* mask of active CRTCs (i.e. DPMS on) */
> bool on; /* is the PLL actually active? Disabled during modeset */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f48e79a..7874f66 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -355,7 +355,7 @@ struct intel_atomic_state {
> /* SKL/KBL Only */
> unsigned int cdclk_pll_vco;
>
> - struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
> + struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
>
> /*
> * Current watermarks can't be trusted during hardware readout, so
> @@ -1798,7 +1798,7 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
> struct drm_crtc_state *state);
> struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
> void intel_atomic_state_clear(struct drm_atomic_state *);
> -struct intel_shared_dpll_config *
> +struct intel_shared_dpll_state *
> intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
>
> static inline struct intel_crtc_state *
> --
> 2.5.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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