On Thu, Oct 13, 2016 at 10:44:44AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> Saves 1392 bytes of .rodata strings.
>
> Also change a few function/macro prototypes in i915_gem_gtt.c
> from dev to dev_priv where it made more sense to do so.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
> v3: Mention function prototype changes. (David Weinhall)
Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> Cc: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
> Acked-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Acked-by: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Acked-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 5 +++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 40 +++++++++++++++++----------------
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++-----------
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++-------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> drivers/gpu/drm/i915/intel_dsi.c | 27 +++++++++++-----------
> drivers/gpu/drm/i915/intel_dsi_pll.c | 26 ++++++++++-----------
> drivers/gpu/drm/i915/intel_guc_loader.c | 8 +++----
> drivers/gpu/drm/i915/intel_hdmi.c | 6 ++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> 13 files changed, 89 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d854ea4a7e92..18af6d1ccec9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2437,7 +2437,7 @@ static int intel_runtime_resume(struct device *kdev)
> if (IS_GEN6(dev_priv))
> intel_init_pch_refclk(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> bxt_display_core_init(dev_priv, true);
> if (dev_priv->csr.dmc_payload &&
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 297f6a103d54..9ad79d196a73 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2667,7 +2667,7 @@ struct drm_i915_cmd_table {
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> -#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
> +#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
> #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
> #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> @@ -2727,7 +2727,8 @@ struct drm_i915_cmd_table {
> #define BXT_REVID_B0 0x3
> #define BXT_REVID_C0 0x9
>
> -#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
> +#define IS_BXT_REVID(dev_priv, since, until) \
> + (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>
> #define KBL_REVID_A0 0x0
> #define KBL_REVID_B0 0x1
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 0b4702cedad1..d215db5e6d38 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -373,27 +373,29 @@ static void *kmap_page_dma(struct i915_page_dma *p)
> /* We use the flushing unmap only with ppgtt structures:
> * page directories, page tables and scratch pages.
> */
> -static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
> +static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr)
> {
> /* There are only few exceptions for gen >=6. chv and bxt.
> * And we are not sure about the latter so play safe for now.
> */
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> drm_clflush_virt_range(vaddr, PAGE_SIZE);
>
> kunmap_atomic(vaddr);
> }
>
> #define kmap_px(px) kmap_page_dma(px_base(px))
> -#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
> +#define kunmap_px(ppgtt, vaddr) \
> + kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr))
>
> #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
> #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
> -#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
> -#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
> +#define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v))
> +#define fill32_px(dev_priv, px, v) \
> + fill_page_dma_32((dev_priv), px_base(px), (v))
>
> -static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> - const uint64_t val)
> +static void fill_page_dma(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint64_t val)
> {
> int i;
> uint64_t * const vaddr = kmap_page_dma(p);
> @@ -401,17 +403,17 @@ static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
> for (i = 0; i < 512; i++)
> vaddr[i] = val;
>
> - kunmap_page_dma(dev, vaddr);
> + kunmap_page_dma(dev_priv, vaddr);
> }
>
> -static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
> - const uint32_t val32)
> +static void fill_page_dma_32(struct drm_i915_private *dev_priv,
> + struct i915_page_dma *p, const uint32_t val32)
> {
> uint64_t v = val32;
>
> v = v << 32 | val32;
>
> - fill_page_dma(dev, p, v);
> + fill_page_dma(dev_priv, p, v);
> }
>
> static int
> @@ -474,7 +476,7 @@ static void gen8_initialize_pt(struct i915_address_space *vm,
> scratch_pte = gen8_pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true);
>
> - fill_px(vm->dev, pt, scratch_pte);
> + fill_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static void gen6_initialize_pt(struct i915_address_space *vm,
> @@ -487,7 +489,7 @@ static void gen6_initialize_pt(struct i915_address_space *vm,
> scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
> I915_CACHE_LLC, true, 0);
>
> - fill32_px(vm->dev, pt, scratch_pte);
> + fill32_px(to_i915(vm->dev), pt, scratch_pte);
> }
>
> static struct i915_page_directory *alloc_pd(struct drm_device *dev)
> @@ -534,7 +536,7 @@ static void gen8_initialize_pd(struct i915_address_space *vm,
>
> scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pd, scratch_pde);
> + fill_px(to_i915(vm->dev), pd, scratch_pde);
> }
>
> static int __pdp_init(struct drm_device *dev,
> @@ -615,7 +617,7 @@ static void gen8_initialize_pdp(struct i915_address_space *vm,
>
> scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
>
> - fill_px(vm->dev, pdp, scratch_pdpe);
> + fill_px(to_i915(vm->dev), pdp, scratch_pdpe);
> }
>
> static void gen8_initialize_pml4(struct i915_address_space *vm,
> @@ -626,7 +628,7 @@ static void gen8_initialize_pml4(struct i915_address_space *vm,
> scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
> I915_CACHE_LLC);
>
> - fill_px(vm->dev, pml4, scratch_pml4e);
> + fill_px(to_i915(vm->dev), pml4, scratch_pml4e);
> }
>
> static void
> @@ -2135,7 +2137,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> }
>
> @@ -2912,7 +2914,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
> * resort to an uncached mapping. The WC issue is easily caught by the
> * readback check when writing GTT PTE entries.
> */
> - if (IS_BROXTON(ggtt->base.dev))
> + if (IS_BROXTON(to_i915(ggtt->base.dev)))
> ggtt->gsm = ioremap_nocache(phys_addr, size);
> else
> ggtt->gsm = ioremap_wc(phys_addr, size);
> @@ -3284,7 +3286,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> ggtt->base.closed = false;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
> + if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
> chv_setup_private_ppat(dev_priv);
> else
> bdw_setup_private_ppat(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index ae43d5ebd76a..a9a73c4b4933 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4597,7 +4597,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->irq_uninstall = gen8_irq_uninstall;
> dev->driver->enable_vblank = gen8_enable_vblank;
> dev->driver->disable_vblank = gen8_disable_vblank;
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 07164e250adf..a76afd7a6616 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2509,7 +2509,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * configuration so that we use the proper lane count for our
> * calculations.
> */
> - if (IS_BROXTON(dev) && port == PORT_A) {
> + if (IS_BROXTON(dev_priv) && port == PORT_A) {
> if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> @@ -2533,7 +2533,7 @@ void intel_ddi_init(struct drm_device *dev, enum port port)
> * On BXT A0/A1, sw needs to activate DDIA HPD logic and
> * interrupts to check the external panel connection.
> */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B)
> dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
> else
> dev_priv->hotplug.irq_port[port] = intel_dig_port;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2c7899000b74..3d2bd5504ab4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -600,7 +600,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock)
> * the given connectors.
> */
>
> -static bool intel_PLL_is_valid(struct drm_device *dev,
> +static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
> const struct intel_limit *limit,
> const struct dpll *clock)
> {
> @@ -613,12 +613,13 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
> INTELPllInvalid("m1 out of range\n");
>
> - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
> + if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> + !IS_BROXTON(dev_priv)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -698,7 +699,8 @@ i9xx_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -753,7 +755,8 @@ pnv_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> pnv_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
> if (match_clock &&
> @@ -813,7 +816,8 @@ g4x_find_best_dpll(const struct intel_limit *limit,
> int this_err;
>
> i9xx_calc_dpll_params(refclk, &clock);
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -909,7 +913,8 @@ vlv_find_best_dpll(const struct intel_limit *limit,
>
> vlv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit,
> + if (!intel_PLL_is_valid(to_i915(dev),
> + limit,
> &clock))
> continue;
>
> @@ -977,7 +982,7 @@ chv_find_best_dpll(const struct intel_limit *limit,
>
> chv_calc_dpll_params(refclk, &clock);
>
> - if (!intel_PLL_is_valid(dev, limit, &clock))
> + if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
> continue;
>
> if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
> @@ -5850,7 +5855,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> max_cdclk = 308571;
>
> dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev_priv)) {
> /*
> @@ -10648,7 +10653,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> haswell_get_ddi_pll(dev_priv, port, pipe_config);
> @@ -12806,7 +12811,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
> DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
> "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
> "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
> @@ -15399,7 +15404,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if (intel_crt_present(dev))
> intel_crt_init(dev);
>
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * FIXME: Broxton doesn't support port detection via the
> * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 02e74c467a55..b6c8b25ee1d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -571,7 +571,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct intel_encoder *encoder;
>
> if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> - !IS_BROXTON(dev)))
> + !IS_BROXTON(dev_priv)))
> return;
>
> /*
> @@ -591,7 +591,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> continue;
>
> intel_dp = enc_to_intel_dp(&encoder->base);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> intel_dp->pps_reset = true;
> else
> intel_dp->pps_pipe = INVALID_PIPE;
> @@ -2981,7 +2981,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = dp_to_dig_port(intel_dp)->port;
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (INTEL_INFO(dev)->gen >= 9) {
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> @@ -3344,7 +3344,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> signal_levels = 0;
> else
> mask = DDI_BUF_EMP_MASK;
> @@ -5072,7 +5072,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5098,7 +5098,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5106,7 +5106,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_BROXTON(dev) ?
> + IS_BROXTON(dev_priv) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> @@ -5715,7 +5715,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> break;
> case PORT_B:
> intel_encoder->hpd_pin = HPD_PORT_B;
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> intel_encoder->hpd_pin = HPD_PORT_A;
> break;
> case PORT_C:
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 7cf9d91c0746..605d0b509f24 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1853,7 +1853,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> dpll_mgr = &skl_pll_mgr;
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> dpll_mgr = &bxt_pll_mgr;
> else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 5b1e445a80d0..48e8dd108f4f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -437,11 +437,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>
> static void intel_dsi_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_device_ready(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_dsi_device_ready(encoder);
> }
>
> @@ -464,7 +464,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -494,7 +494,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> u32 temp;
>
> @@ -656,7 +656,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
>
> static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> @@ -664,7 +663,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> DRM_DEBUG_KMS("\n");
> for_each_dsi_port(port, intel_dsi->ports) {
> /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
> - i915_reg_t port_ctrl = IS_BROXTON(dev) ?
> + i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
> u32 val;
>
> @@ -762,7 +761,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>
> /* XXX: this only works for one DSI output */
> for_each_dsi_port(port, intel_dsi->ports) {
> - i915_reg_t ctrl_reg = IS_BROXTON(dev) ?
> + i915_reg_t ctrl_reg = IS_BROXTON(dev_priv) ?
> BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
> bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
>
> @@ -970,11 +969,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
> static void intel_dsi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> u32 pclk;
> DRM_DEBUG_KMS("\n");
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_get_pipe_config(encoder, pipe_config);
>
> pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
> @@ -1066,7 +1065,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
> hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_BROXTON(dev)) {
> + if (IS_BROXTON(dev_priv)) {
> /*
> * Program hdisplay and vdisplay on MIPI transcoder.
> * This is different from calculated hactive and
> @@ -1153,7 +1152,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> tmp &= ~READ_REQUEST_PRIORITY_MASK;
> I915_WRITE(MIPI_CTRL(port), tmp |
> READ_REQUEST_PRIORITY_HIGH);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> enum pipe pipe = intel_crtc->pipe;
>
> tmp = I915_READ(MIPI_CTRL(port));
> @@ -1242,7 +1241,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> I915_WRITE(MIPI_INIT_COUNT(port),
> txclkesc(intel_dsi->escape_clk_div, 100));
>
> - if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) {
> + if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
> /*
> * BXT spec says write MIPI_INIT_COUNT for
> * both the ports, even if only one is
> @@ -1452,7 +1451,7 @@ void intel_dsi_init(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> } else {
> DRM_ERROR("Unsupported Mipi device to reg base");
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 6ab58a01b18e..56eff6004bc0 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -351,7 +351,7 @@ static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
> struct intel_crtc_state *config)
> {
> - if (IS_BROXTON(encoder->base.dev))
> + if (IS_BROXTON(to_i915(encoder->base.dev)))
> return bxt_dsi_get_pclk(encoder, pipe_bpp, config);
> else
> return vlv_dsi_get_pclk(encoder, pipe_bpp, config);
> @@ -515,11 +515,11 @@ bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> int intel_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> return bxt_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> @@ -528,21 +528,21 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> void intel_enable_dsi_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *config)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_enable_dsi_pll(encoder, config);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_enable_dsi_pll(encoder, config);
> }
>
> void intel_disable_dsi_pll(struct intel_encoder *encoder)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_disable_dsi_pll(encoder);
> - else if (IS_BROXTON(dev))
> + else if (IS_BROXTON(dev_priv))
> bxt_disable_dsi_pll(encoder);
> }
>
> @@ -564,10 +564,10 @@ static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>
> void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> bxt_dsi_reset_clocks(encoder, port);
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_dsi_reset_clocks(encoder, port);
> }
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 182204373931..5d5d609ed5e9 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -376,16 +376,16 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
>
> /* WaDisableMinuteIaClockGating:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
> ~GUC_ENABLE_MIA_CLOCK_GATING));
> }
>
> /* WaC6DisallowByGfxPause:bxt */
> - if (IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev_priv))
> I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> @@ -730,7 +730,7 @@ void intel_guc_init(struct drm_device *dev)
> fw_path = I915_SKL_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = SKL_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = SKL_FW_MINOR;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> fw_path = I915_BXT_GUC_UCODE;
> guc_fw->guc_fw_major_wanted = BXT_FW_MAJOR;
> guc_fw->guc_fw_minor_wanted = BXT_FW_MINOR;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 6607c4e3c36c..f6562451c47e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1241,7 +1241,7 @@ static enum drm_mode_status
> hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> int clock, bool respect_downstream_limits)
> {
> - struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> + struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
>
> if (clock < 25000)
> return MODE_CLOCK_LOW;
> @@ -1249,11 +1249,11 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> return MODE_CLOCK_HIGH;
>
> /* BXT DPLL can't generate 223-240 MHz */
> - if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
> + if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> /* CHV DPLL can't generate 216-240 MHz */
> - if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
> + if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
> return MODE_CLOCK_RANGE;
>
> return MODE_OK;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 025fbd522819..e4bb85c9c6e1 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2596,7 +2596,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> skl_display_core_init(dev_priv, resume);
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> } else if (IS_CHERRYVIEW(dev)) {
> mutex_lock(&power_domains->lock);
> --
> 2.7.4
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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