On Tue, Oct 11, 2016 at 02:21:49PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> Saves 864 bytes of .rodata strings and ~100 of .text.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 8 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
> drivers/gpu/drm/i915/intel_audio.c | 4 +-
> drivers/gpu/drm/i915/intel_color.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 67 +++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 55 ++++++++++++++-------------
> drivers/gpu/drm/i915/intel_dsi.c | 8 ++--
> drivers/gpu/drm/i915/intel_hdmi.c | 10 ++---
> drivers/gpu/drm/i915/intel_i2c.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +-
> drivers/gpu/drm/i915/intel_sprite.c | 10 +++--
> 14 files changed, 93 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 18af6d1ccec9..5e7b6a1cb2c8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -424,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev)
> u32 temp;
> bool enabled;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return;
>
> dev_priv->mchbar_need_disable = false;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f54465ea2f44..96846ecfc224 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2660,7 +2660,7 @@ struct drm_i915_cmd_table {
> INTEL_DEVID(dev_priv) == 0x0152 || \
> INTEL_DEVID(dev_priv) == 0x015a)
> #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
> -#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
> +#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
> #define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
> #define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
> #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
> @@ -3838,11 +3838,11 @@ __raw_write(64, q)
> #define INTEL_BROADCAST_RGB_FULL 1
> #define INTEL_BROADCAST_RGB_LIMITED 2
>
> -static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
> +static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
> {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return VLV_VGACNTRL;
> - else if (INTEL_INFO(dev)->gen >= 5)
> + else if (INTEL_GEN(dev_priv) >= 5)
> return CPU_VGACNTRL;
> else
> return VGACNTRL;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e628691fe97e..4211b9a4a918 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2133,7 +2133,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
> /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> else if (IS_SKYLAKE(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
> index 13b726916f98..d1275cbd5905 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -428,8 +428,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
> aud_config = IBX_AUD_CFG(pipe);
> aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
> aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
> - } else if (IS_VALLEYVIEW(connector->dev) ||
> - IS_CHERRYVIEW(connector->dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) {
> hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
> aud_config = VLV_AUD_CFG(pipe);
> aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index da76a799411a..445108855275 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -534,7 +534,7 @@ void intel_color_init(struct drm_crtc *crtc)
>
> drm_mode_crtc_set_gamma_size(crtc, 256);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;
> dev_priv->display.load_luts = cherryview_load_luts;
> } else if (IS_HASWELL(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bf871b565549..d61a12dbbd72 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -849,7 +849,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
> * For CHV ignore the error and consider only the P value.
> * Prefer a bigger P value based on HW requirements.
> */
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(to_i915(dev))) {
> *error_ppm = 0;
>
> return calculated_clock->p > best_clock->p;
> @@ -1332,7 +1332,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
> "plane %d assertion failure, should be off on pipe %c but is still active\n",
> sprite, pipe_name(pipe));
> }
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> for_each_sprite(dev_priv, pipe, sprite) {
> u32 val = I915_READ(SPCNTR(pipe, sprite));
> I915_STATE_WARN(val & SP_ENABLE,
> @@ -3033,7 +3033,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> I915_WRITE(DSPPOS(plane), 0);
> - } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
> + } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> I915_WRITE(PRIMSIZE(plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> @@ -5874,7 +5874,7 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = 540000;
> else
> dev_priv->max_cdclk_freq = 675000;
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> dev_priv->max_cdclk_freq = 320000;
> } else if (IS_VALLEYVIEW(dev)) {
> dev_priv->max_cdclk_freq = 400000;
> @@ -6676,7 +6676,7 @@ static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> */
> intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> cherryview_set_cdclk(dev, req_cdclk);
> else
> valleyview_set_cdclk(dev, req_cdclk);
> @@ -6704,7 +6704,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
> intel_set_pipe_timings(intel_crtc);
> intel_set_pipe_src_size(intel_crtc);
>
> - if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
> @@ -6719,7 +6719,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> chv_prepare_pll(intel_crtc, intel_crtc->config);
> chv_enable_pll(intel_crtc, intel_crtc->config);
> } else {
> @@ -6838,7 +6838,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> intel_encoders_post_disable(crtc, old_crtc_state, old_state);
>
> if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> chv_disable_pll(dev_priv, pipe);
> else if (IS_VALLEYVIEW(dev))
> vlv_disable_pll(dev_priv, pipe);
> @@ -7805,8 +7805,8 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
> * for gen < 8) and if DRRS is supported (to make sure the
> * registers are not unnecessarily accessed).
> */
> - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
> - crtc->config->has_drrs) {
> + if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
> + INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
> I915_WRITE(PIPE_DATA_M2(transcoder),
> TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
> I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
> @@ -8108,7 +8108,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> pipe_config->pixel_multiplier = 1;
> pipe_config->dpll = *dpll;
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(to_i915(dev))) {
> chv_compute_dpll(crtc, pipe_config);
> chv_prepare_pll(crtc, pipe_config);
> chv_enable_pll(crtc, pipe_config);
> @@ -8133,7 +8133,7 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
> */
> void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
> {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(to_i915(dev)))
> chv_disable_pll(to_i915(dev), pipe);
> else
> vlv_disable_pll(to_i915(dev), pipe);
> @@ -8457,7 +8457,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
> } else
> pipeconf |= PIPECONF_PROGRESSIVE;
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_crtc->config->limited_color_range)
> pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
>
> @@ -8851,7 +8851,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> }
> }
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> (tmp & PIPECONF_COLOR_RANGE_SELECT))
> pipe_config->limited_color_range = true;
>
> @@ -8865,7 +8865,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* No way to read it out on pipes B and C */
> - if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
> + if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
> tmp = dev_priv->chv_dpll_md[crtc->pipe];
> else
> tmp = I915_READ(DPLL_MD(crtc->pipe));
> @@ -8886,7 +8886,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
> pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> /*
> * DPLL_DVO_2X_MODE must be enabled for both DPLLs
> * on 830. Filter it out here so that we don't
> @@ -8904,7 +8904,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> DPLL_PORTB_READY_MASK);
> }
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> chv_crtc_clock_get(crtc, pipe_config);
> else if (IS_VALLEYVIEW(dev))
> vlv_crtc_clock_get(crtc, pipe_config);
> @@ -12250,7 +12250,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> engine = &dev_priv->engine[BCS];
> if (fb->modifier[0] != old_fb->modifier[0])
> /* vlv: DISPLAY_FLIP fails to change tiling */
> @@ -13348,7 +13348,7 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_I(pixel_multiplier);
> PIPE_CONF_CHECK_I(has_hdmi_sink);
> if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
> - IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> PIPE_CONF_CHECK_I(limited_color_range);
> PIPE_CONF_CHECK_I(has_infoframe);
>
> @@ -15068,7 +15068,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
> * display power well must be turned off and on again.
> * Refuse the put the cursor into that compromised position.
> */
> - if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
> + if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C &&
> state->base.visible && state->base.crtc_x < 0) {
> DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
> return -EINVAL;
> @@ -15338,7 +15338,7 @@ static bool intel_crt_present(struct drm_device *dev)
> if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
> return false;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> return false;
>
> if (HAS_PCH_LPT_H(dev_priv) &&
> @@ -15479,7 +15479,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (I915_READ(PCH_DP_D) & DP_DETECTED)
> intel_dp_init(dev, PCH_DP_D, PORT_D);
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> bool has_edp, has_port;
>
> /*
> @@ -15511,7 +15511,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
> intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
>
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> /*
> * eDP not supported on port D,
> * so no need to worry about it
> @@ -15629,10 +15629,10 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> };
>
> static
> -u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> - uint32_t pixel_format)
> +u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> + uint64_t fb_modifier, uint32_t pixel_format)
> {
> - u32 gen = INTEL_INFO(dev)->gen;
> + u32 gen = INTEL_INFO(dev_priv)->gen;
>
> if (gen >= 9) {
> int cpp = drm_format_plane_cpp(pixel_format, 0);
> @@ -15641,7 +15641,8 @@ u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
> * pixels and 32K bytes."
> */
> return min(8192 * cpp, 32768);
> - } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) &&
> + !IS_CHERRYVIEW(dev_priv)) {
> return 32*1024;
> } else if (gen >= 4) {
> if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> @@ -15728,7 +15729,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> return -EINVAL;
> }
>
> - pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
> + pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
> mode_cmd->pixel_format);
> if (mode_cmd->pitches[0] > pitch_limit) {
> DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
> @@ -15766,7 +15767,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> }
> break;
> case DRM_FORMAT_ABGR8888:
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> INTEL_INFO(dev)->gen < 9) {
> format_name = drm_get_format_name(mode_cmd->pixel_format);
> DRM_DEBUG("unsupported pixel format: %s\n", format_name);
> @@ -15785,7 +15786,7 @@ static int intel_framebuffer_init(struct drm_device *dev,
> }
> break;
> case DRM_FORMAT_ABGR2101010:
> - if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
> + if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
> format_name = drm_get_format_name(mode_cmd->pixel_format);
> DRM_DEBUG("unsupported pixel format: %s\n", format_name);
> kfree(format_name);
> @@ -16232,7 +16233,7 @@ static void i915_disable_vga(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct pci_dev *pdev = dev_priv->drm.pdev;
> u8 sr1;
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
> + i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
>
> /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
> vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> @@ -16677,7 +16678,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
> void i915_redisable_vga_power_on(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
> + i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
>
> if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> @@ -16915,7 +16916,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> pll->on = false;
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_wm_get_hw_state(dev);
> else if (IS_GEN9(dev))
> skl_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dfc93cc11a13..1e1ccf092e11 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -344,7 +344,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> DP |= DP_PORT_WIDTH(1);
> DP |= DP_LINK_TRAIN_PAT_1;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> DP |= DP_PIPE_SELECT_CHV(pipe);
> else if (pipe == PIPE_B)
> DP |= DP_PIPEB_SELECT;
> @@ -356,10 +356,10 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp)
> * So enable temporarily it if it's not already enabled.
> */
> if (!pll_enabled) {
> - release_cl_override = IS_CHERRYVIEW(dev) &&
> + release_cl_override = IS_CHERRYVIEW(dev_priv) &&
> !chv_phy_powergate_ch(dev_priv, phy, ch, true);
>
> - if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
> + if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
> &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
> DRM_ERROR("Failed to force on pll for pipe %c!\n",
> pipe_name(pipe));
> @@ -570,7 +570,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
> struct drm_device *dev = &dev_priv->drm;
> struct intel_encoder *encoder;
>
> - if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
> + if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
> !IS_BROXTON(dev_priv)))
> return;
>
> @@ -664,7 +664,7 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>
> pps_lock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
> i915_reg_t pp_ctrl_reg, pp_div_reg;
> u32 pp_div;
> @@ -692,7 +692,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_dp->pps_pipe == INVALID_PIPE)
> return false;
>
> @@ -706,7 +706,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
>
> lockdep_assert_held(&dev_priv->pps_mutex);
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> intel_dp->pps_pipe == INVALID_PIPE)
> return false;
>
> @@ -1347,7 +1347,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> divisor = pch_dpll;
> count = ARRAY_SIZE(pch_dpll);
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> divisor = chv_dpll;
> count = ARRAY_SIZE(chv_dpll);
> } else if (IS_VALLEYVIEW(dev)) {
> @@ -1791,7 +1791,8 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> } else {
> if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
> - !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
> + !IS_CHERRYVIEW(dev_priv) &&
> + pipe_config->limited_color_range)
> intel_dp->DP |= DP_COLOR_RANGE_16_235;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> @@ -1803,7 +1804,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> intel_dp->DP |= DP_ENHANCED_FRAMING;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> else if (crtc->pipe == PIPE_B)
> intel_dp->DP |= DP_PIPEB_SELECT;
> @@ -2459,7 +2460,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
> i915_mmio_reg_offset(intel_dp->output_reg));
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> *pipe = DP_PORT_TO_PIPE_CHV(tmp);
> } else {
> *pipe = PORT_TO_PIPE(tmp);
> @@ -2681,7 +2682,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
>
> } else {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> else
> *DP &= ~DP_LINK_TRAIN_MASK;
> @@ -2697,7 +2698,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> *DP |= DP_LINK_TRAIN_PAT_2;
> break;
> case DP_TRAINING_PATTERN_3:
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> } else {
> DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
> @@ -2747,7 +2748,7 @@ static void intel_enable_dp(struct intel_encoder *encoder,
>
> pps_lock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_init_panel_power_sequencer(intel_dp);
>
> intel_dp_enable_port(intel_dp, pipe_config);
> @@ -2758,10 +2759,10 @@ static void intel_enable_dp(struct intel_encoder *encoder,
>
> pps_unlock(intel_dp);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> unsigned int lane_mask = 0x0;
>
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
>
> vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
> @@ -2987,7 +2988,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> else if (IS_GEN7(dev) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> @@ -3348,7 +3349,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> signal_levels = 0;
> else
> mask = DDI_BUF_EMP_MASK;
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev)) {
> signal_levels = vlv_signal_levels(intel_dp);
> @@ -3448,7 +3449,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> } else {
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> DP &= ~DP_LINK_TRAIN_MASK_CHV;
> else
> DP &= ~DP_LINK_TRAIN_MASK;
> @@ -5085,7 +5086,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequencer any more. */
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> port_sel = PANEL_PORT_SELECT_VLV(port);
> } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
> if (port == PORT_A)
> @@ -5114,7 +5115,9 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> static void intel_dp_pps_init(struct drm_device *dev,
> struct intel_dp *intel_dp)
> {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> vlv_initial_power_sequencer_setup(intel_dp);
> } else {
> intel_dp_init_panel_power_sequencer(dev, intel_dp);
> @@ -5584,7 +5587,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> }
> mutex_unlock(&dev->mode_config.mutex);
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_dp->edp_notifier.notifier_call = edp_notify_handler;
> register_reboot_notifier(&intel_dp->edp_notifier);
>
> @@ -5593,7 +5596,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
> * If the current pipe isn't valid, try the PPS pipe, and if that
> * fails just assume pipe A.
> */
> - if (IS_CHERRYVIEW(dev))
> + if (IS_CHERRYVIEW(dev_priv))
> pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
> else
> pipe = PORT_TO_PIPE(intel_dp->DP);
> @@ -5682,7 +5685,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> intel_encoder->type = INTEL_OUTPUT_EDP;
>
> /* eDP only on port B and/or C on vlv/chv */
> - if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> is_edp(intel_dp) && port != PORT_B && port != PORT_C))
> return false;
>
> @@ -5792,7 +5795,7 @@ bool intel_dp_init(struct drm_device *dev,
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
> intel_encoder->pre_enable = chv_pre_enable_dp;
> intel_encoder->enable = vlv_enable_dp;
> @@ -5815,7 +5818,7 @@ bool intel_dp_init(struct drm_device *dev,
> intel_dig_port->max_lanes = 4;
>
> intel_encoder->type = INTEL_OUTPUT_DP;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> intel_encoder->crtc_mask = 1 << 2;
> else
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 48e8dd108f4f..4e0d025490a3 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -740,7 +740,6 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> enum intel_display_power_domain power_domain;
> enum port port;
> bool active = false;
> @@ -770,7 +769,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> * bit in port C control register does not get set. As a
> * workaround, check pipe B conf instead.
> */
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C)
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + port == PORT_C)
> enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
>
> /* Try command mode if video mode not enabled */
> @@ -1137,7 +1137,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> /*
> * escape clock divider, 20MHz, shared for A and C.
> * device ready must be off when doing this! txclkesc?
> @@ -1449,7 +1449,7 @@ void intel_dsi_init(struct drm_device *dev)
> if (!intel_bios_is_dsi_present(dev_priv, &port))
> return;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
> } else if (IS_BROXTON(dev_priv)) {
> dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index c7d9cddf4e3e..c8243dc4d2b9 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -881,7 +881,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
>
> if (HAS_PCH_CPT(dev_priv))
> hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
> else
> hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
> @@ -913,7 +913,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
>
> if (HAS_PCH_CPT(dev_priv))
> *pipe = PORT_TO_PIPE_CPT(tmp);
> - else if (IS_CHERRYVIEW(dev))
> + else if (IS_CHERRYVIEW(dev_priv))
> *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
> else
> *pipe = PORT_TO_PIPE(tmp);
> @@ -1885,7 +1885,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> BUG();
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_hdmi->write_infoframe = vlv_write_infoframe;
> intel_hdmi->set_infoframes = vlv_set_infoframes;
> intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
> @@ -1959,7 +1959,7 @@ void intel_hdmi_init(struct drm_device *dev,
> }
> intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
> intel_encoder->get_config = intel_hdmi_get_config;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
> intel_encoder->pre_enable = chv_hdmi_pre_enable;
> intel_encoder->enable = vlv_enable_hdmi;
> @@ -1982,7 +1982,7 @@ void intel_hdmi_init(struct drm_device *dev,
>
> intel_encoder->type = INTEL_OUTPUT_HDMI;
> intel_encoder->port = port;
> - if (IS_CHERRYVIEW(dev)) {
> + if (IS_CHERRYVIEW(dev_priv)) {
> if (port == PORT_D)
> intel_encoder->crtc_mask = 1 << 2;
> else
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index afb2652919d0..d04185e1edd6 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -635,7 +635,7 @@ int intel_setup_gmbus(struct drm_device *dev)
> if (HAS_PCH_NOP(dev_priv))
> return 0;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> else if (!HAS_GMCH_DISPLAY(dev_priv))
> dev_priv->gpio_mmio_base =
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2c5dcd3ba2c2..2107434a42e4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -322,7 +322,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> struct drm_device *dev = &dev_priv->drm;
> u32 val;
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> POSTING_READ(FW_BLC_SELF_VLV);
> dev_priv->wm.vlv.cxsr = enable;
> @@ -7755,7 +7755,7 @@ void intel_init_pm(struct drm_device *dev)
> DRM_DEBUG_KMS("Failed to read display plane latency. "
> "Disable CxSR\n");
> }
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev);
> dev_priv->display.update_wm = vlv_update_wm;
> } else if (IS_VALLEYVIEW(dev)) {
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 4a973b34348a..271a3e29ff23 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -354,7 +354,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> return false;
> }
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> !dev_priv->psr.link_standby) {
> DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n");
> return false;
> @@ -837,7 +837,7 @@ void intel_psr_init(struct drm_device *dev)
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> /* HSW and BDW require workarounds that we don't implement. */
> dev_priv->psr.link_standby = false;
> - else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
> + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> /* On VLV and CHV only standby mode is supported. */
> dev_priv->psr.link_standby = true;
> else
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e4bb85c9c6e1..3a6e1a93aed9 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2598,7 +2598,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> skl_display_core_init(dev_priv, resume);
> } else if (IS_BROXTON(dev_priv)) {
> bxt_display_core_init(dev_priv, resume);
> - } else if (IS_CHERRYVIEW(dev)) {
> + } else if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> mutex_unlock(&power_domains->lock);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index fefd3034aead..f760d5fcbe48 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -450,7 +450,7 @@ vlv_update_plane(struct drm_plane *dplane,
> if (key->flags & I915_SET_COLORKEY_SOURCE)
> sprctl |= SP_SOURCE_KEY;
>
> - if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
> + if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
> chv_update_csc(intel_plane, fb->pixel_format);
>
> I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
> @@ -944,6 +944,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
> int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> struct drm_file *file_priv)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_intel_sprite_colorkey *set = data;
> struct drm_plane *plane;
> struct drm_plane_state *plane_state;
> @@ -955,7 +956,7 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
> if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
> return -EINVAL;
>
> - if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> set->flags & I915_SET_COLORKEY_DESTINATION)
> return -EINVAL;
>
> @@ -1042,6 +1043,7 @@ static uint32_t skl_plane_formats[] = {
> int
> intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_plane *intel_plane = NULL;
> struct intel_plane_state *state = NULL;
> unsigned long possible_crtcs;
> @@ -1084,7 +1086,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
>
> case 7:
> case 8:
> - if (IS_IVYBRIDGE(to_i915(dev))) {
> + if (IS_IVYBRIDGE(dev_priv)) {
> intel_plane->can_scale = true;
> intel_plane->max_downscale = 2;
> } else {
> @@ -1092,7 +1094,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> intel_plane->max_downscale = 1;
> }
>
> - if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> intel_plane->update_plane = vlv_update_plane;
> intel_plane->disable_plane = vlv_disable_plane;
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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