On Tue, Oct 11, 2016 at 02:21:52PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> Saves 1416 bytes of .rodata strings.
>
> v2: Add parantheses around dev_priv. (Ville Syrjala)
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
Do note though, that this is a *very* large patch, and I suspect that
you'll have trouble getting it merged...
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.c | 6 +--
> drivers/gpu/drm/i915/i915_drv.h | 16 +++---
> drivers/gpu/drm/i915/i915_gem.c | 8 +--
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_fence.c | 9 ++--
> drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++--
> drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++--
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_suspend.c | 4 +-
> drivers/gpu/drm/i915/intel_crt.c | 6 +--
> drivers/gpu/drm/i915/intel_display.c | 41 ++++++++-------
> drivers/gpu/drm/i915/intel_dp.c | 20 +++----
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +--
> drivers/gpu/drm/i915/intel_guc_loader.c | 3 +-
> drivers/gpu/drm/i915/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 83 +++++++++++++++---------------
> drivers/gpu/drm/i915/intel_sprite.c | 4 +-
> 21 files changed, 126 insertions(+), 124 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 20689f1cd719..3a42df3a29e5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4552,7 +4552,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
> else if (IS_VALLEYVIEW(dev_priv))
> num_levels = 1;
> else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>
> drm_modeset_lock_all(dev);
>
> @@ -4668,7 +4668,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
> else if (IS_VALLEYVIEW(dev_priv))
> num_levels = 1;
> else
> - num_levels = ilk_wm_max_level(dev) + 1;
> + num_levels = ilk_wm_max_level(dev_priv) + 1;
>
> if (len >= sizeof(tmp))
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5e7b6a1cb2c8..c1956855feb6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -174,7 +174,7 @@ static void intel_detect_pch(struct drm_device *dev)
> if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_IBX;
> DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
> - WARN_ON(!IS_GEN5(dev));
> + WARN_ON(!IS_GEN5(dev_priv));
> } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
> dev_priv->pch_type = PCH_CPT;
> DRM_DEBUG_KMS("Found CougarPoint PCH\n");
> @@ -884,7 +884,7 @@ static int i915_mmio_setup(struct drm_device *dev)
> int mmio_bar;
> int mmio_size;
>
> - mmio_bar = IS_GEN2(dev) ? 1 : 0;
> + mmio_bar = IS_GEN2(dev_priv) ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -1037,7 +1037,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
> pci_set_master(pdev);
>
> /* overlay on gen2 is broken and can't address above 1G */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
> if (ret) {
> DRM_ERROR("failed to set DMA mask\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3f38b9755763..a05665af31be 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2742,14 +2742,14 @@ struct drm_i915_cmd_table {
> * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
> * chips, etc.).
> */
> -#define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
> -#define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
> -#define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
> -#define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
> -#define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
> -#define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
> -#define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
> -#define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
> +#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
> +#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
> +#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
> +#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
> +#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
> +#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
> +#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
> +#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
>
> #define ENGINE_MASK(id) BIT(id)
> #define RENDER_RING ENGINE_MASK(RCS)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 8c362899674a..b79392605256 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4308,15 +4308,15 @@ void i915_gem_init_swizzling(struct drm_device *dev)
> I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> DISP_TILE_SURFACE_SWIZZLING);
>
> - if (IS_GEN5(dev))
> + if (IS_GEN5(dev_priv))
> return;
>
> I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
> - else if (IS_GEN8(dev))
> + else if (IS_GEN8(dev_priv))
> I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
> else
> BUG();
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 72c7c1855e70..11bb3ae94e00 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -572,7 +572,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_relocation_entry *reloc,
> struct reloc_cache *cache)
> {
> - struct drm_device *dev = obj->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
> struct drm_gem_object *target_obj;
> struct drm_i915_gem_object *target_i915_obj;
> struct i915_vma *target_vma;
> @@ -591,7 +591,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
> /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
> * pipe_control writes because the gpu doesn't properly redirect them
> * through the ppgtt for non_secure batchbuffers. */
> - if (unlikely(IS_GEN6(dev) &&
> + if (unlikely(IS_GEN6(dev_priv) &&
> reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
> ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
> PIN_GLOBAL);
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
> index d26768567252..bedf2278df16 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence.c
> +++ b/drivers/gpu/drm/i915/i915_gem_fence.c
> @@ -487,19 +487,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> }
> }
> - } else if (IS_GEN5(dev)) {
> + } else if (IS_GEN5(dev_priv)) {
> /* On Ironlake whatever DRAM config, GPU always do
> * same swizzling setup.
> */
> swizzle_x = I915_BIT_6_SWIZZLE_9_10;
> swizzle_y = I915_BIT_6_SWIZZLE_9;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> /* As far as we know, the 865 doesn't have these bit 6
> * swizzling issues.
> */
> swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> - } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
> + } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
> + !IS_G33(dev_priv))) {
> uint32_t dcc;
>
> /* On 9xx chipsets, channel interleave by the CPU is
> @@ -537,7 +538,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
> }
>
> /* check for L-shaped memory aka modified enhanced addressing */
> - if (IS_GEN4(dev) &&
> + if (IS_GEN4(dev_priv) &&
> !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
> swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
> swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4211b9a4a918..c35ba67d1a5d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2058,11 +2058,11 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
> int ret;
>
> ppgtt->base.pte_encode = ggtt->base.pte_encode;
> - if (intel_vgpu_active(dev_priv) || IS_GEN6(dev))
> + if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
> ppgtt->switch_mm = gen6_mm_switch;
> else if (IS_HASWELL(dev_priv))
> ppgtt->switch_mm = hsw_mm_switch;
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ppgtt->switch_mm = gen7_mm_switch;
> else
> BUG();
> @@ -2159,6 +2159,8 @@ static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
>
> int i915_ppgtt_init_hw(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> gtt_write_workarounds(dev);
>
> /* In the case of execlists, PPGTT is enabled by the context descriptor
> @@ -2170,9 +2172,9 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
> if (!USES_PPGTT(dev))
> return 0;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> gen6_ppgtt_enable(dev);
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> gen7_ppgtt_enable(dev);
> else if (INTEL_INFO(dev)->gen >= 8)
> gen8_ppgtt_enable(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index d1b40bce0249..f4f6d3a48b05 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -215,7 +215,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> u64 ggtt_start, ggtt_end;
>
> ggtt_start = I915_READ(PGTBL_CTL);
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
> (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
> else
> @@ -271,7 +271,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
> * GEN3 firmware likes to smash pci bridges into the stolen
> * range. Apparently this works.
> */
> - if (r == NULL && !IS_GEN3(dev)) {
> + if (r == NULL && !IS_GEN3(dev_priv)) {
> DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
> base, base + (uint32_t)ggtt->stolen_size);
> base = 0;
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 89d1d234a1b4..c21bc0068d20 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -72,7 +72,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> if (tiling_mode > I915_TILING_LAST)
> return false;
>
> - if (IS_GEN2(dev) ||
> + if (IS_GEN2(dev_priv) ||
> (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))
> tile_width = 128;
> else
> @@ -91,7 +91,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
> if (stride > 8192)
> return false;
>
> - if (IS_GEN3(dev)) {
> + if (IS_GEN3(dev_priv)) {
> if (size > I830_FENCE_MAX_SIZE_VAL << 20)
> return false;
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 6eb11fd326fd..629ac567dcbb 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -442,7 +442,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
> err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
> }
>
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
>
> for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
> @@ -1355,7 +1355,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
> }
>
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> error->err_int = I915_READ(GEN7_ERR_INT);
>
> if (INTEL_INFO(dev)->gen >= 8) {
> @@ -1363,7 +1363,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> }
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> error->forcewake = I915_READ_FW(FORCEWAKE);
> error->gab_ctl = I915_READ(GAB_CTL);
> error->gfx_mode = I915_READ(GFX_MODE);
> @@ -1380,7 +1380,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> }
>
> /* 3: Feature specific registers */
> - if (IS_GEN6(dev) || IS_GEN7(dev)) {
> + if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
> error->gam_ecochk = I915_READ(GAM_ECOCHK);
> error->gac_eco = I915_READ(GAC_ECO_BITS);
> }
> @@ -1396,7 +1396,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> error->ier = I915_READ(DEIER);
> error->gtier[0] = I915_READ(GTIER);
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> error->ier = I915_READ16(IER);
> } else if (!IS_VALLEYVIEW(dev_priv)) {
> error->ier = I915_READ(IER);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 079ba7cfc971..d610df92ad1f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3333,7 +3333,7 @@ static void ironlake_irq_reset(struct drm_device *dev)
> I915_WRITE(HWSTAM, 0xffffffff);
>
> GEN5_IRQ_RESET(DE);
> - if (IS_GEN7(dev))
> + if (IS_GEN7(dev_priv))
> I915_WRITE(GEN7_ERR_INT, 0xffffffff);
>
> gen5_gt_irq_reset(dev);
> @@ -3599,7 +3599,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
> }
>
> gt_irqs |= GT_RENDER_USER_INTERRUPT;
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> gt_irqs |= ILK_BSD_USER_INTERRUPT;
> } else {
> gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 7870856fccd0..344cbf39cfa9 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -70,7 +70,7 @@ int i915_save_state(struct drm_device *dev)
>
> i915_save_display(dev);
>
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> pci_read_config_word(pdev, GCDGMBUS,
> &dev_priv->regfile.saveGCDGMBUS);
>
> @@ -116,7 +116,7 @@ int i915_restore_state(struct drm_device *dev)
>
> i915_gem_restore_fences(dev);
>
> - if (IS_GEN4(dev))
> + if (IS_GEN4(dev_priv))
> pci_write_config_word(pdev, GCDGMBUS,
> dev_priv->regfile.saveGCDGMBUS);
> i915_restore_display(dev);
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index d92c3edf10ff..a97151fcb9f4 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -259,7 +259,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> * DAC limit supposedly 355 MHz.
> */
> max_clock = 270000;
> - else if (IS_GEN3(dev) || IS_GEN4(dev))
> + else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv))
> max_clock = 400000;
> else
> max_clock = 350000;
> @@ -567,7 +567,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
> /* Set the border color to purple. */
> I915_WRITE(bclrpat_reg, 0x500050);
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> uint32_t pipeconf = I915_READ(pipeconf_reg);
> I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
> POSTING_READ(pipeconf_reg);
> @@ -899,7 +899,7 @@ void intel_crt_init(struct drm_device *dev)
> else
> crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> connector->interlace_allowed = 0;
> else
> connector->interlace_allowed = 1;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index eda38e53f68a..f3931c66116f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1045,7 +1045,7 @@ static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
> u32 line1, line2;
> u32 line_mask;
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> line_mask = DSL_LINEMASK_GEN2;
> else
> line_mask = DSL_LINEMASK_GEN3;
> @@ -3947,7 +3947,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> temp = I915_READ(reg);
> temp &= ~FDI_LINK_TRAIN_NONE;
> temp |= FDI_LINK_TRAIN_PATTERN_2;
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
> /* SNB-B */
> temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> @@ -4985,7 +4985,7 @@ intel_post_enable_primary(struct drm_crtc *crtc)
> * FIXME: Need to fix the logic to work when we turn off all planes
> * but leave the pipe running.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> /* Underruns don't always raise interrupts, so check manually. */
> @@ -5008,7 +5008,7 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
> * FIXME: Need to fix the logic to work when we turn off all planes
> * but leave the pipe running.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> /*
> @@ -6775,7 +6775,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
>
> intel_crtc->active = true;
>
> - if (!IS_GEN2(dev))
> + if (!IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
>
> intel_encoders_pre_enable(crtc, pipe_config, old_state);
> @@ -6823,7 +6823,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
> * On gen2 planes are double buffered but the pipe isn't, so we must
> * wait for planes to fully turn off before disabling the pipe.
> */
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> intel_wait_for_vblank(dev, pipe);
>
> intel_encoders_disable(crtc, old_crtc_state, old_state);
> @@ -6848,7 +6848,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
>
> intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
>
> - if (!IS_GEN2(dev))
> + if (!IS_GEN2(dev_priv))
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
> }
>
> @@ -9846,7 +9846,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
> /* We currently do not free assignements of panel fitters on
> * ivb/hsw (since we don't use the higher upscaling modes which
> * differentiates them) so just WARN about this case for now. */
> - if (IS_GEN7(dev)) {
> + if (IS_GEN7(dev_priv)) {
> WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
> PF_PIPE_SEL_IVB(crtc->pipe));
> }
> @@ -11322,7 +11322,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
> return dev_priv->vbt.lvds_ssc_freq;
> else if (HAS_PCH_SPLIT(dev_priv))
> return 120000;
> - else if (!IS_GEN2(dev))
> + else if (!IS_GEN2(dev_priv))
> return 96000;
> else
> return 48000;
> @@ -11355,7 +11355,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
> }
>
> - if (!IS_GEN2(dev)) {
> + if (!IS_GEN2(dev_priv)) {
> if (IS_PINEVIEW(dev))
> clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
> @@ -11854,6 +11854,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_ring *ring = req->ring;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t plane_bit = 0;
> @@ -11882,7 +11883,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> * 48bits addresses, and we need a NOOP for the batch size to
> * stay even.
> */
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> len += 2;
> }
>
> @@ -11919,7 +11920,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
> DERRMR_PIPEB_PRI_FLIP_DONE |
> DERRMR_PIPEC_PRI_FLIP_DONE));
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
> MI_SRM_LRM_GLOBAL_GTT);
> else
> @@ -11928,7 +11929,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> intel_ring_emit_reg(ring, DERRMR);
> intel_ring_emit(ring,
> i915_ggtt_offset(req->engine->scratch) + 256);
> - if (IS_GEN8(dev)) {
> + if (IS_GEN8(dev_priv)) {
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> }
> @@ -15322,7 +15323,7 @@ static bool has_edp_a(struct drm_device *dev)
> if ((I915_READ(DP_A) & DP_DETECTED) == 0)
> return false;
>
> - if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
> + if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
> return false;
>
> return true;
> @@ -15524,7 +15525,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> }
>
> intel_dsi_init(dev);
> - } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
> + } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
> bool found = false;
>
> if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
> @@ -15558,7 +15559,7 @@ static void intel_setup_outputs(struct drm_device *dev)
>
> if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
> intel_dp_init(dev, DP_D, PORT_D);
> - } else if (IS_GEN2(dev))
> + } else if (IS_GEN2(dev_priv))
> intel_dvo_init(dev);
>
> if (SUPPORTS_TV(dev))
> @@ -16383,10 +16384,10 @@ void intel_modeset_init(struct drm_device *dev)
> }
> }
>
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> dev->mode_config.max_width = 2048;
> dev->mode_config.max_height = 2048;
> - } else if (IS_GEN3(dev)) {
> + } else if (IS_GEN3(dev_priv)) {
> dev->mode_config.max_width = 4096;
> dev->mode_config.max_height = 4096;
> } else {
> @@ -16397,7 +16398,7 @@ void intel_modeset_init(struct drm_device *dev)
> if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
> dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
> dev->mode_config.cursor_height = 1023;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
> dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
> } else {
> @@ -16918,7 +16919,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> vlv_wm_get_hw_state(dev);
> - else if (IS_GEN9(dev))
> + else if (IS_GEN9(dev_priv))
> skl_wm_get_hw_state(dev);
> else if (HAS_PCH_SPLIT(dev_priv))
> ilk_wm_get_hw_state(dev);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a2c4d5a0b704..ba3ac2661625 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1767,7 +1767,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
>
> /* Split out the IBX/CPU vs CPT settings */
>
> - if (IS_GEN7(dev) && port == PORT_A) {
> + if (IS_GEN7(dev_priv) && port == PORT_A) {
> if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
> intel_dp->DP |= DP_SYNC_HS_HIGH;
> if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -2113,7 +2113,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
>
> pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
> pp = ironlake_get_pp_control(intel_dp);
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> /* ILK workaround: disable reset around power sequence */
> pp &= ~PANEL_POWER_RESET;
> I915_WRITE(pp_ctrl_reg, pp);
> @@ -2121,7 +2121,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
> }
>
> pp |= PANEL_POWER_ON;
> - if (!IS_GEN5(dev))
> + if (!IS_GEN5(dev_priv))
> pp |= PANEL_POWER_RESET;
>
> I915_WRITE(pp_ctrl_reg, pp);
> @@ -2130,7 +2130,7 @@ static void edp_panel_on(struct intel_dp *intel_dp)
> wait_panel_on(intel_dp);
> intel_dp->last_power_on = jiffies;
>
> - if (IS_GEN5(dev)) {
> + if (IS_GEN5(dev_priv)) {
> pp |= PANEL_POWER_RESET; /* restore panel reset bit */
> I915_WRITE(pp_ctrl_reg, pp);
> POSTING_READ(pp_ctrl_reg);
> @@ -2443,7 +2443,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
> if (!(tmp & DP_PORT_EN))
> goto out;
>
> - if (IS_GEN7(dev) && port == PORT_A) {
> + if (IS_GEN7(dev_priv) && port == PORT_A) {
> *pipe = PORT_TO_PIPE_CPT(tmp);
> } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
> enum pipe p;
> @@ -2661,7 +2661,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> }
> I915_WRITE(DP_TP_CTL(port), temp);
>
> - } else if ((IS_GEN7(dev) && port == PORT_A) ||
> + } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> *DP &= ~DP_LINK_TRAIN_MASK_CPT;
>
> @@ -2990,7 +2990,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - else if (IS_GEN7(dev) && port == PORT_A)
> + else if (IS_GEN7(dev_priv) && port == PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> @@ -3353,10 +3353,10 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> signal_levels = chv_signal_levels(intel_dp);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> signal_levels = vlv_signal_levels(intel_dp);
> - } else if (IS_GEN7(dev) && port == PORT_A) {
> + } else if (IS_GEN7(dev_priv) && port == PORT_A) {
> signal_levels = gen7_edp_signal_levels(train_set);
> mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
> - } else if (IS_GEN6(dev) && port == PORT_A) {
> + } else if (IS_GEN6(dev_priv) && port == PORT_A) {
> signal_levels = gen6_edp_signal_levels(train_set);
> mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
> } else {
> @@ -3444,7 +3444,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>
> DRM_DEBUG_KMS("\n");
>
> - if ((IS_GEN7(dev) && port == PORT_A) ||
> + if ((IS_GEN7(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> DP &= ~DP_LINK_TRAIN_MASK_CPT;
> DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index f48e79ae2ac6..9f571770c1db 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1722,7 +1722,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> /* intel_pm.c */
> void intel_init_clock_gating(struct drm_device *dev);
> void intel_suspend_hw(struct drm_device *dev);
> -int ilk_wm_max_level(const struct drm_device *dev);
> +int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> void intel_update_watermarks(struct drm_crtc *crtc);
> void intel_init_pm(struct drm_device *dev);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> index 076893cc3890..3018f4f589c8 100644
> --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
> @@ -256,11 +256,11 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
>
> if (HAS_GMCH_DISPLAY(dev_priv))
> i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
> - else if (IS_GEN5(dev) || IS_GEN6(dev))
> + else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
> ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
> - else if (IS_GEN7(dev))
> + else if (IS_GEN7(dev_priv))
> ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
> - else if (IS_GEN8(dev) || IS_GEN9(dev))
> + else if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
> broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
>
> return old;
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 5d5d609ed5e9..cc7df0c57982 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -347,7 +347,6 @@ static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
> static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> {
> struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
> - struct drm_device *dev = &dev_priv->drm;
> struct i915_vma *vma;
> int ret;
>
> @@ -390,7 +389,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
> else
> I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
>
> - if (IS_GEN9(dev)) {
> + if (IS_GEN9(dev_priv)) {
> /* DOP Clock Gating Enable for GuC clocks */
> I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
> I915_READ(GEN7_MISCCPCTL)));
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 1c47f99917e6..199b90c7907a 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -1071,7 +1071,7 @@ void intel_lvds_init(struct drm_device *dev)
> intel_encoder->cloneable = 0;
> if (HAS_PCH_SPLIT(dev_priv))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> - else if (IS_GEN4(dev))
> + else if (IS_GEN4(dev_priv))
> intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
> else
> intel_encoder->crtc_mask = (1 << 1);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9baffae4f9f8..d9eb10f2bb78 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1530,7 +1530,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
>
> if (IS_I945GM(dev))
> wm_info = &i945_wm_info;
> - else if (!IS_GEN2(dev))
> + else if (!IS_GEN2(dev_priv))
> wm_info = &i915_wm_info;
> else
> wm_info = &i830_a_wm_info;
> @@ -1540,7 +1540,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> cpp = 4;
>
> adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> @@ -1554,7 +1554,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> planea_wm = wm_info->max_wm;
> }
>
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> wm_info = &i830_bc_wm_info;
>
> fifo_size = dev_priv->display.get_fifo_size(dev, 1);
> @@ -1562,7 +1562,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *adjusted_mode;
> int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
> - if (IS_GEN2(dev))
> + if (IS_GEN2(dev_priv))
> cpp = 4;
>
> adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
> @@ -2082,10 +2082,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (IS_GEN9(dev)) {
> + if (IS_GEN9(dev_priv)) {
> uint32_t val;
> int ret, i;
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> @@ -2184,10 +2184,11 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
> }
> }
>
> -static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
> + uint16_t wm[5])
> {
> /* ILK sprite LP0 latency is 1300 ns */
> - if (IS_GEN5(dev))
> + if (IS_GEN5(dev_priv))
> wm[0] = 13;
> }
>
> @@ -2203,10 +2204,8 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
> wm[3] *= 2;
> }
>
> -int ilk_wm_max_level(const struct drm_device *dev)
> +int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> -
> /* how many WM levels are we expecting */
> if (INTEL_GEN(dev_priv) >= 9)
> return 7;
> @@ -2218,11 +2217,11 @@ int ilk_wm_max_level(const struct drm_device *dev)
> return 2;
> }
>
> -static void intel_print_wm_latency(struct drm_device *dev,
> +static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
> const char *name,
> const uint16_t wm[8])
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> for (level = 0; level <= max_level; level++) {
> unsigned int latency = wm[level];
> @@ -2237,7 +2236,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
> * - latencies are in us on gen9.
> * - before then, WM1+ latency values are in 0.5us units
> */
> - if (IS_GEN9(dev))
> + if (IS_GEN9(dev_priv))
> latency *= 10;
> else if (level > 0)
> latency *= 5;
> @@ -2251,7 +2250,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
> static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
> uint16_t wm[5], uint16_t min)
> {
> - int level, max_level = ilk_wm_max_level(&dev_priv->drm);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> if (wm[0] >= min)
> return false;
> @@ -2280,9 +2279,9 @@ static void snb_wm_latency_quirk(struct drm_device *dev)
> return;
>
> DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
> - intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> - intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> - intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
> }
>
> static void ilk_setup_wm_latency(struct drm_device *dev)
> @@ -2296,14 +2295,14 @@ static void ilk_setup_wm_latency(struct drm_device *dev)
> memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
> sizeof(dev_priv->wm.pri_latency));
>
> - intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
> + intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
> intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
>
> - intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
> - intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
> - intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> snb_wm_latency_quirk(dev);
> }
>
> @@ -2312,7 +2311,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
> - intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
> + intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
> }
>
> static bool ilk_validate_pipe_wm(struct drm_device *dev,
> @@ -2350,7 +2349,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
> struct intel_plane_state *pristate = NULL;
> struct intel_plane_state *sprstate = NULL;
> struct intel_plane_state *curstate = NULL;
> - int level, max_level = ilk_wm_max_level(dev), usable_level;
> + int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
> struct ilk_wm_maximums max;
>
> pipe_wm = &cstate->wm.ilk.optimal;
> @@ -2437,7 +2436,7 @@ static int ilk_compute_intermediate_wm(struct drm_device *dev,
> {
> struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
> struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
>
> /*
> * Start with the final, target watermarks, then combine with the
> @@ -2521,7 +2520,7 @@ static void ilk_wm_merge(struct drm_device *dev,
> struct intel_pipe_wm *merged)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> int last_enabled_level = max_level;
>
> /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
> @@ -2561,7 +2560,7 @@ static void ilk_wm_merge(struct drm_device *dev,
> * What we should check here is whether FBC can be
> * enabled sometime later.
> */
> - if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
> + if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
> intel_fbc_is_active(dev_priv)) {
> for (level = 2; level <= max_level; level++) {
> struct intel_wm_level *wm = &merged->wm[level];
> @@ -2661,7 +2660,7 @@ static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
> struct intel_pipe_wm *r1,
> struct intel_pipe_wm *r2)
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
> int level1 = 0, level2 = 0;
>
> for (level = 1; level <= max_level; level++) {
> @@ -3035,7 +3034,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
> continue;
>
> /* Find the highest enabled wm level for this plane */
> - for (level = ilk_wm_max_level(dev);
> + for (level = ilk_wm_max_level(dev_priv);
> intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
> { }
>
> @@ -3776,7 +3775,7 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
> {
> struct drm_device *dev = cstate->base.crtc->dev;
> const struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> int ret;
>
> for (level = 0; level <= max_level; level++) {
> @@ -3797,7 +3796,7 @@ static void skl_compute_wm_results(struct drm_device *dev,
> struct skl_wm_values *r,
> struct intel_crtc *intel_crtc)
> {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(to_i915(dev));
> enum pipe pipe = intel_crtc->pipe;
> uint32_t temp;
> int i;
> @@ -3866,7 +3865,7 @@ void skl_write_plane_wm(struct intel_crtc *intel_crtc,
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> enum pipe pipe = intel_crtc->pipe;
>
> for (level = 0; level <= max_level; level++) {
> @@ -3887,7 +3886,7 @@ void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> struct drm_crtc *crtc = &intel_crtc->base;
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
> enum pipe pipe = intel_crtc->pipe;
>
> for (level = 0; level <= max_level; level++) {
> @@ -4331,7 +4330,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> int level, i, max_level;
> uint32_t temp;
>
> - max_level = ilk_wm_max_level(dev);
> + max_level = ilk_wm_max_level(dev_priv);
>
> hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
>
> @@ -4431,7 +4430,7 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
> active->linetime = hw->wm_linetime[pipe];
> } else {
> - int level, max_level = ilk_wm_max_level(dev);
> + int level, max_level = ilk_wm_max_level(dev_priv);
>
> /*
> * For inactive pipes, all watermark levels
> @@ -7729,7 +7728,7 @@ void intel_init_pm(struct drm_device *dev)
> /* For cxsr */
> if (IS_PINEVIEW(dev))
> i915_pineview_get_mem_freq(dev);
> - else if (IS_GEN5(dev))
> + else if (IS_GEN5(dev_priv))
> i915_ironlake_get_mem_freq(dev);
>
> /* For FIFO watermark updates */
> @@ -7740,9 +7739,9 @@ void intel_init_pm(struct drm_device *dev)
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev);
>
> - if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
> + if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
> dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
> - (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
> + (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
> dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> dev_priv->display.compute_intermediate_wm =
> @@ -7778,12 +7777,12 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->display.update_wm = pineview_update_wm;
> } else if (IS_G4X(dev_priv)) {
> dev_priv->display.update_wm = g4x_update_wm;
> - } else if (IS_GEN4(dev)) {
> + } else if (IS_GEN4(dev_priv)) {
> dev_priv->display.update_wm = i965_update_wm;
> - } else if (IS_GEN3(dev)) {
> + } else if (IS_GEN3(dev_priv)) {
> dev_priv->display.update_wm = i9xx_update_wm;
> dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
> - } else if (IS_GEN2(dev)) {
> + } else if (IS_GEN2(dev_priv)) {
> if (INTEL_INFO(dev)->num_pipes == 1) {
> dev_priv->display.update_wm = i845_update_wm;
> dev_priv->display.get_fifo_size = i845_get_fifo_size;
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8b4748839c07..c7d9a20e370d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -680,7 +680,7 @@ ilk_update_plane(struct drm_plane *plane,
> if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
> dvscntr |= DVS_TILED;
>
> - if (IS_GEN6(dev))
> + if (IS_GEN6(dev_priv))
> dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
>
> /* Sizes are 0 based */
> @@ -1075,7 +1075,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
> intel_plane->update_plane = ilk_update_plane;
> intel_plane->disable_plane = ilk_disable_plane;
>
> - if (IS_GEN6(dev)) {
> + if (IS_GEN6(dev_priv)) {
> plane_formats = snb_plane_formats;
> num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> } else {
> --
> 2.7.4
>
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