Op 10-10-16 om 11:57 schreef Chris Wilson: > On Mon, Oct 10, 2016 at 11:35:07AM +0200, Maarten Lankhorst wrote: >> Op 07-10-16 om 21:49 schreef Chris Wilson: >>> To enable the vblank itself, we need to have an RPM wakeref for the mmio >>> access, and whilst generating the vblank interrupts we continue to >>> require the rpm wakeref. The assumption is that the RPM wakeref is held >>> by the display powerwell held by the active pipe. As this chain was not >>> obvious to me chasing the drm_wait_vblank ioctl, document it with a WARN >>> during *_vblank_enable(). >>> >>> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> >>> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >>> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> >> Don't we prevent enabling the vblank irq through drm_crtc_vblank_on/off? > Should, but this is the boundary point from the midlayer, so > sanitychecks ahoy. > >> I'd rather not have things look at crtc->state if possible, locking might not help you. > Ok, anything better? > -Chris I would say either intel_display_is_enabled(POWER_DOMAIN_PIPE(pipe)) or assert_rpm_wakelock_held. ~Maarten _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
