This adds support in the kernel to handle link training compliance requests and send a uevent to train at requested parameters. In this patch series, if the link training fails in modeset, then a hotplug uevent is added to a work queue and scheduled and failed link parameters are stored in intel_dp structure. This uevent gets executed after the modeset is completed and after locks are released. In the modeset retry, modes are validated based on lower link rate from the failed link rate value to prune the modes in intel_dp_mode_valid(). The lower link rate is then used toc onfigure the pipe and link is retrained at this lower link rate. I have tested this with DPR-120 and the compliance tests are passing. The DP CTS spec is based on DP 1.2 spec and it only expects to reduce the link rate and train at the max lane count without reducing the lane count. Lane count reduction is added in DP 1.3 so Unigraf has agreed to add it to their next SW release. Hence I have not implemented fallback for lane count. But I can add it if you think we should add DP 1.3 link training algorithm. Please let me know your feedback on this. Compliance app is not required for link training tests and so I have tested this fallback using kernel console mode on Source DUT. Manasi Navare (4): drm/i915; Add a function to return index of link rate drm/i915: Add support for DP link training compliance drm/i915: Link Rate fallback on Link training failure drm/i915: Work queue for uevent Navare, Manasi D (1): drm/i915: Change the placement of some static functions in intel_dp.c drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/intel_ddi.c | 10 +- drivers/gpu/drm/i915/intel_dp.c | 277 ++++++++++++++++++-------- drivers/gpu/drm/i915/intel_dp_link_training.c | 12 +- drivers/gpu/drm/i915/intel_drv.h | 8 +- 5 files changed, 217 insertions(+), 92 deletions(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
