On Wed, Oct 05, 2016 at 01:33:31PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
>
> This saves 3248 bytes of .rodata strings.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 8 +++---
> drivers/gpu/drm/i915/intel_crt.c | 10 +++----
> drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++------
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +--
> drivers/gpu/drm/i915/intel_hdmi.c | 10 +++----
> drivers/gpu/drm/i915/intel_pm.c | 4 +--
> drivers/gpu/drm/i915/intel_psr.c | 8 +++---
> 8 files changed, 56 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 4613f031d127..61e0cf7374ed 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2817,7 +2817,7 @@ struct drm_i915_cmd_table {
>
> #define HAS_DP_MST(dev) (INTEL_INFO(dev)->has_dp_mst)
>
> -#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> +#define HAS_DDI(dev_priv) (dev_priv->info.has_ddi)
((dev_priv)->...)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
> @@ -2856,8 +2856,10 @@ struct drm_i915_cmd_table {
> #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
> #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_LP(dev_priv) \
> + (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev_priv) \
> + (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 88ebbdde185a..227eaf270226 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -280,13 +280,13 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - if (HAS_PCH_SPLIT(dev))
> + if (HAS_PCH_SPLIT(dev_priv))
> pipe_config->has_pch_encoder = true;
>
> /* LPT FDI RX only supports 8bpc. */
> - if (HAS_PCH_LPT(dev)) {
> + if (HAS_PCH_LPT(dev_priv)) {
> if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
> DRM_DEBUG_KMS("LPT only supports 24bpp\n");
> return false;
> @@ -296,7 +296,7 @@ static bool intel_crt_compute_config(struct intel_encoder *encoder,
> }
>
> /* FDI must always be 2.7 GHz */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> pipe_config->port_clock = 135000 * 2;
>
> return true;
> @@ -916,7 +916,7 @@ void intel_crt_init(struct drm_device *dev)
> crt->base.enable = intel_enable_crt;
> if (I915_HAS_HOTPLUG(dev))
> crt->base.hpd_pin = HPD_CRT;
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> crt->base.port = PORT_E;
> crt->base.get_config = hsw_crt_get_config;
> crt->base.get_hw_state = intel_ddi_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a366656bcec5..235df123ac50 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1187,19 +1187,17 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
> onoff(state), onoff(cur_state));
> }
>
> -void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> - enum pipe pipe)
> +void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - struct drm_device *dev = &dev_priv->drm;
> i915_reg_t pp_reg;
> u32 val;
> enum pipe panel_pipe = PIPE_A;
> bool locked = true;
>
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
> return;
>
> - if (HAS_PCH_SPLIT(dev)) {
> + if (HAS_PCH_SPLIT(dev_priv)) {
> u32 port_sel;
>
> pp_reg = PP_CONTROL(0);
> @@ -1209,7 +1207,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
> panel_pipe = PIPE_B;
> /* XXX: else fix for eDP */
> - } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> /* presumably write lock depends on pipe, not port select */
> pp_reg = PP_CONTROL(pipe);
> panel_pipe = pipe;
> @@ -5695,13 +5693,13 @@ static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
> enum intel_display_power_domain
> intel_display_port_power_domain(struct intel_encoder *intel_encoder)
> {
> - struct drm_device *dev = intel_encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> struct intel_digital_port *intel_dig_port;
>
> switch (intel_encoder->type) {
> case INTEL_OUTPUT_UNKNOWN:
> /* Only DDI platforms should ever use this output type */
> - WARN_ON_ONCE(!HAS_DDI(dev));
> + WARN_ON_ONCE(!HAS_DDI(dev_priv));
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_HDMI:
> case INTEL_OUTPUT_EDP:
> @@ -5722,7 +5720,7 @@ intel_display_port_power_domain(struct intel_encoder *intel_encoder)
> enum intel_display_power_domain
> intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
> {
> - struct drm_device *dev = intel_encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
> struct intel_digital_port *intel_dig_port;
>
> switch (intel_encoder->type) {
> @@ -5735,7 +5733,7 @@ intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
> * what's the status of the given connectors, play safe and
> * run the DP detection too.
> */
> - WARN_ON_ONCE(!HAS_DDI(dev));
> + WARN_ON_ONCE(!HAS_DDI(dev_priv));
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_EDP:
> intel_dig_port = enc_to_dig_port(&intel_encoder->base);
> @@ -9195,7 +9193,8 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
>
> if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
> with_spread = true;
> - if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
> + if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
> + with_fdi, "LP PCH doesn't have FDI\n"))
> with_fdi = false;
>
> mutex_lock(&dev_priv->sb_lock);
> @@ -9218,7 +9217,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
> }
> }
>
> - reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> @@ -9234,7 +9233,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
>
> mutex_lock(&dev_priv->sb_lock);
>
> - reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
> + reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
> tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
> tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
> intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
> @@ -10202,7 +10201,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv)
>
> DRM_DEBUG_KMS("Enabling package C8+\n");
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> val = I915_READ(SOUTH_DSPCLK_GATE_D);
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> @@ -10222,7 +10221,7 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> hsw_restore_lcpll(dev_priv);
> lpt_init_pch_refclk(dev);
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> val = I915_READ(SOUTH_DSPCLK_GATE_D);
> val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> @@ -10844,7 +10843,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
> }
> cntl |= pipe << 28; /* Connect to correct pipe */
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> cntl |= CURSOR_PIPE_CSC_ENABLE;
>
> if (plane_state->base.rotation == DRM_ROTATE_180)
> @@ -12744,6 +12743,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> const char *context)
> {
> struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_plane *plane;
> struct intel_plane *intel_plane;
> struct intel_plane_state *state;
> @@ -12826,7 +12826,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
> pipe_config->dpll_hw_state.ctrl1,
> pipe_config->dpll_hw_state.cfgcr1,
> pipe_config->dpll_hw_state.cfgcr2);
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
> pipe_config->dpll_hw_state.wrpll,
> pipe_config->dpll_hw_state.spll);
> @@ -12904,7 +12904,7 @@ static bool check_digital_port_conflicts(struct drm_atomic_state *state)
> switch (encoder->type) {
> unsigned int port_mask;
> case INTEL_OUTPUT_UNKNOWN:
> - if (WARN_ON(!HAS_DDI(dev)))
> + if (WARN_ON(!HAS_DDI(to_i915(dev))))
> break;
> case INTEL_OUTPUT_DP:
> case INTEL_OUTPUT_HDMI:
> @@ -13728,7 +13728,7 @@ intel_modeset_verify_disabled(struct drm_device *dev)
>
> static void update_scanline_offset(struct intel_crtc *crtc)
> {
> - struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> /*
> * The scanline counter increments at the leading edge of hsync.
> @@ -13748,7 +13748,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
> * there's an extra 1 line difference. So we need to add two instead of
> * one to the value.
> */
> - if (IS_GEN2(dev)) {
> + if (IS_GEN2(dev_priv)) {
> const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
> int vtotal;
>
> @@ -13757,7 +13757,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
> vtotal /= 2;
>
> crtc->scanline_offset = vtotal - 1;
> - } else if (HAS_DDI(dev) &&
> + } else if (HAS_DDI(dev_priv) &&
> intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
> crtc->scanline_offset = 2;
> } else
> @@ -15326,11 +15326,12 @@ static bool intel_crt_present(struct drm_device *dev)
> if (IS_CHERRYVIEW(dev))
> return false;
>
> - if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
> + if (HAS_PCH_LPT_H(dev_priv) &&
> + I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
> return false;
>
> /* DDI E can't be used if DDI A requires 4 lanes */
> - if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> + if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> return false;
>
> if (!dev_priv->vbt.int_crt_support)
> @@ -15404,7 +15405,7 @@ static void intel_setup_outputs(struct drm_device *dev)
> intel_ddi_init(dev, PORT_C);
>
> intel_dsi_init(dev);
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> int found;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5992093e1814..edaf35b975c0 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1565,7 +1565,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>
> max_clock = common_len - 1;
>
> - if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
> pipe_config->has_pch_encoder = true;
>
> pipe_config->has_drrs = false;
> @@ -1707,7 +1707,7 @@ found:
> to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
> }
>
> - if (!HAS_DDI(dev))
> + if (!HAS_DDI(dev_priv))
> intel_dp_set_clock(encoder, pipe_config);
>
> return true;
> @@ -2632,7 +2632,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
> dp_train_pat & DP_TRAINING_PATTERN_MASK);
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> uint32_t temp = I915_READ(DP_TP_CTL(port));
>
> if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> @@ -3339,7 +3339,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> uint32_t signal_levels, mask = 0;
> uint8_t train_set = intel_dp->train_set[0];
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> signal_levels = ddi_signal_levels(intel_dp);
>
> if (IS_BROXTON(dev))
> @@ -3398,7 +3398,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> enum port port = intel_dig_port->port;
> uint32_t val;
>
> - if (!HAS_DDI(dev))
> + if (!HAS_DDI(dev_priv))
> return;
>
> val = I915_READ(DP_TP_CTL(port));
> @@ -3433,7 +3433,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = to_i915(dev);
> uint32_t DP = intel_dp->DP;
>
> - if (WARN_ON(HAS_DDI(dev)))
> + if (WARN_ON(HAS_DDI(dev_priv)))
> return;
>
> if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
> @@ -5659,7 +5659,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> else
> intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
>
> /* Preserve the current hw state. */
> @@ -5701,7 +5701,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>
> intel_connector_attach_encoder(intel_connector, intel_encoder);
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> else
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 1c59ca50c430..d0c59c1793ef 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1855,7 +1855,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> dpll_mgr = &skl_pll_mgr;
> else if (IS_BROXTON(dev))
> dpll_mgr = &bxt_pll_mgr;
> - else if (HAS_DDI(dev))
> + else if (HAS_DDI(dev_priv))
> dpll_mgr = &hsw_pll_mgr;
> else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> dpll_mgr = &pch_pll_mgr;
> @@ -1883,7 +1883,7 @@ void intel_shared_dpll_init(struct drm_device *dev)
> BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
>
> /* FIXME: Move this to a more suitable place */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_ddi_pll_init(dev);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 8d46f5836746..09b2146f157f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -50,7 +50,7 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
> struct drm_i915_private *dev_priv = to_i915(dev);
> uint32_t enabled_bits;
>
> - enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
> + enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
>
> WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
> "HDMI port enabled, expecting disabled\n");
> @@ -1312,7 +1312,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> struct drm_connector_state *conn_state)
> {
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
> - struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
> int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
> int clock_12bpc = clock_8bpc * 3 / 2;
> @@ -1339,7 +1339,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
> clock_12bpc *= 2;
> }
>
> - if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
> + if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
> pipe_config->has_pch_encoder = true;
>
> if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
> @@ -1892,7 +1892,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->write_infoframe = g4x_write_infoframe;
> intel_hdmi->set_infoframes = g4x_set_infoframes;
> intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
> - } else if (HAS_DDI(dev)) {
> + } else if (HAS_DDI(dev_priv)) {
> intel_hdmi->write_infoframe = hsw_write_infoframe;
> intel_hdmi->set_infoframes = hsw_set_infoframes;
> intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
> @@ -1906,7 +1906,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
> intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
> }
>
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
> else
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 96d0c57c816c..f29491077235 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7132,7 +7132,7 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> * TODO: this bit should only be enabled when really needed, then
> * disabled when not needed anymore in order to save power.
> */
> - if (HAS_PCH_LPT_LP(dev))
> + if (HAS_PCH_LPT_LP(dev_priv))
> I915_WRITE(SOUTH_DSPCLK_GATE_D,
> I915_READ(SOUTH_DSPCLK_GATE_D) |
> PCH_LP_PARTITION_LEVEL_DISABLE);
> @@ -7147,7 +7147,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - if (HAS_PCH_LPT_LP(dev)) {
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
>
> val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 108ba1e5d658..9e2fbac9776e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -344,7 +344,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> * ones. Since by Display design transcoder EDP is tied to port A
> * we can safely escape based on the port A.
> */
> - if (HAS_DDI(dev) && dig_port->port != PORT_A) {
> + if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) {
> DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");
> return false;
> }
> @@ -402,7 +402,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> lockdep_assert_held(&dev_priv->psr.lock);
>
> /* Enable/Re-enable PSR on the host */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> /* On HSW+ after we enable PSR on source it will activate it
> * as soon as it match configure idle_frame count. So
> * we just actually enable it here on activation time.
> @@ -448,7 +448,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>
> dev_priv->psr.busy_frontbuffer_bits = 0;
>
> - if (HAS_DDI(dev)) {
> + if (HAS_DDI(dev_priv)) {
> hsw_psr_setup_vsc(intel_dp);
>
> if (dev_priv->psr.psr2_support) {
> @@ -580,7 +580,7 @@ void intel_psr_disable(struct intel_dp *intel_dp)
> }
>
> /* Disable PSR on Source */
> - if (HAS_DDI(dev))
> + if (HAS_DDI(dev_priv))
> hsw_psr_disable(intel_dp);
> else
> vlv_psr_disable(intel_dp);
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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