This patch series includes some of the remaining patches to enable
upfront link training on DDI platforms for DP SST and MST.
They are based on some of the patches submitted earlier by
Ander and Durgadoss.
The upfront link training had to be factored out of long pulse
hanlder because of deadlock issues seen on DP MST cases.
Now the upfront link training takes place in intel_dp_mode_valid()
to find the maximum lane count and link rate at which the DP link
can be successfully trained. These values are used to prune the
invalid modes before modeset. Modeset makes use the upfront lane
count and link train values.
These patches have been validated for DP SST and DP MST on DDI
platforms.
The existing implementation of link training does not implement fallback
for link rate/lane count as per the DP spec.
This patch series implements fallback loop to lower link rate
and lane count on CR and/or Channel EQ failures during link training.
Jim Bride (1):
drm/i915/dp/mst: Add support for upfront link training for DP MST
Manasi Navare (4):
drm/i915: Fallback to lower link rate and lane count during link
training
drm/i915: Remove the link rate and lane count loop in compute config
drm/i915: Change the placement of some static functions in intel_dp.c
drm/i915/dp: Enable Upfront link training on DDI platforms
drivers/gpu/drm/i915/intel_ddi.c | 129 ++++++++-
drivers/gpu/drm/i915/intel_dp.c | 386 +++++++++++++++++++-------
drivers/gpu/drm/i915/intel_dp_link_training.c | 13 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 74 +++--
drivers/gpu/drm/i915/intel_drv.h | 21 +-
5 files changed, 490 insertions(+), 133 deletions(-)
--
1.9.1
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