Op 12-09-16 om 13:02 schreef Maarten Lankhorst:
> Op 09-09-16 om 10:01 schreef Kumar, Mahesh:
>> From: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
>>
>> This patch implemnets Workarounds related to display arbitrated memory
>> bandwidth. These WA are applicabe for all gen-9 based platforms.
>>
>> Changes since v1:
>> - Rebase on top of Paulo's patch series
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 9 +++
>> drivers/gpu/drm/i915/intel_drv.h | 11 +++
>> drivers/gpu/drm/i915/intel_pm.c | 145 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 165 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 4313992..4737a0e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1074,6 +1074,13 @@ enum intel_sbi_destination {
>> SBI_MPHY,
>> };
>>
>> +/* SKL+ Watermark arbitrated display bandwidth Workarounds */
>> +enum watermark_memory_wa {
>> + WATERMARK_WA_NONE,
>> + WATERMARK_WA_X_TILED,
>> + WATERMARK_WA_Y_TILED,
>> +};
>> +
>> #define QUIRK_PIPEA_FORCE (1<<0)
>> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
>> #define QUIRK_INVERT_BRIGHTNESS (1<<2)
>> @@ -1623,6 +1630,8 @@ struct skl_ddb_allocation {
>>
>> struct skl_wm_values {
>> unsigned dirty_pipes;
>> + /* any WaterMark memory workaround Required */
>> + enum watermark_memory_wa mem_wa;
>> struct skl_ddb_allocation ddb;
>> uint32_t wm_linetime[I915_MAX_PIPES];
>> uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 6cd7e8a..66cb46c 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1800,6 +1800,17 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>> return to_intel_crtc_state(crtc_state);
>> }
>>
>> +static inline struct intel_crtc_state *
>> +intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
>> + struct intel_crtc *crtc)
>> +{
>> + struct drm_crtc_state *crtc_state;
>> +
>> + crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
>> +
>> + return to_intel_crtc_state(crtc_state);
>> +}
>> +
>> static inline struct intel_plane_state *
>> intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
>> struct intel_plane *plane)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 7c70e07..0ec328b 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3589,6 +3589,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> {
>> struct drm_plane_state *pstate = &intel_pstate->base;
>> struct drm_framebuffer *fb = pstate->fb;
>> + struct intel_atomic_state *intel_state =
>> + to_intel_atomic_state(cstate->base.state);
>> uint32_t latency = dev_priv->wm.skl_latency[level];
>> uint32_t method1, method2;
>> uint32_t plane_bytes_per_line, plane_blocks_per_line;
>> @@ -3602,10 +3604,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> struct skl_wm_level *result = &pipe_wm->wm[level];
>> uint16_t *out_blocks = &result->plane_res_b[id];
>> uint8_t *out_lines = &result->plane_res_l[id];
>> + enum watermark_memory_wa mem_wa;
>>
>> if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible)
>> return 0;
>>
>> + mem_wa = intel_state ? intel_state->wm_results.mem_wa : WATERMARK_WA_NONE;
>> + if (mem_wa != WATERMARK_WA_NONE) {
>> + if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
>> + latency += 15;
>> + }
>> +
>> width = drm_rect_width(&intel_pstate->base.src) >> 16;
>> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>>
>> @@ -3637,6 +3646,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
>> y_min_scanlines = 4;
>> }
>>
>> + if (mem_wa == WATERMARK_WA_Y_TILED)
>> + y_min_scanlines *= 2;
>> +
>> plane_bytes_per_line = width * cpp;
>> if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
>> fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
> I don't have y_min_scanlines in nightly? What is this series based on?
> It doesn't apply cleanly at least..
Ah nevermind, applies on top of Paulo's series.
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