From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Add slpc_param_id enum values.
Add events for setting/unsetting parameters.
v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)
v2: Checkpatch update.
v3: Rebase.
v4: Updated with GuC firmware v9.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_slpc.c | 102 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 32 +++++++++++-
2 files changed, 133 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 2aa2ba4..84b0423 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -65,6 +65,108 @@ static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
host2guc_slpc(dev_priv, data, 4);
}
+static void host2guc_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id, u32 value)
+{
+ u32 data[4];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2);
+ data[2] = (u32) id;
+ data[3] = value;
+
+ host2guc_slpc(dev_priv, data, 4);
+}
+
+static void host2guc_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id)
+{
+ u32 data[3];
+
+ data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+ data[1] = SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1);
+ data[2] = (u32) id;
+
+ host2guc_slpc(dev_priv, data, 3);
+}
+
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ &= (~(1 << (id % 32)));
+ data->override_parameters_values[id] = 0;
+ kunmap_atomic(data);
+
+ host2guc_slpc_unset_param(dev_priv, id);
+ }
+}
+
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ u32 value)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ data->override_parameters_set_bits[id >> 5]
+ |= (1 << (id % 32));
+ data->override_parameters_values[id] = value;
+ kunmap_atomic(data);
+
+ host2guc_slpc_set_param(dev_priv, id, value);
+ }
+}
+
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ int *overriding, u32 *value)
+{
+ struct drm_i915_gem_object *obj;
+ struct page *page;
+ struct slpc_shared_data *data = NULL;
+ u32 bits;
+
+ obj = dev_priv->guc.slpc.vma->obj;
+ if (obj) {
+ page = i915_gem_object_get_page(obj, 0);
+ if (page)
+ data = kmap_atomic(page);
+ }
+
+ if (data) {
+ if (overriding) {
+ bits = data->override_parameters_set_bits[id >> 5];
+ *overriding = (0 != (bits & (1 << (id % 32))));
+ }
+ if (value)
+ *value = data->override_parameters_values[id];
+
+ kunmap_atomic(data);
+ }
+}
+
static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
{
enum slpc_platform_sku platform_sku;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 4838e1e..b0a627d 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -64,6 +64,29 @@ enum slpc_event_id {
#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
#define SLPC_EVENT_STATUS_MASK 0xFF
+enum slpc_param_id {
+ SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+ SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+ SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+ SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+ SLPC_PARAM_TASK_ENABLE_DCC = 4,
+ SLPC_PARAM_TASK_DISABLE_DCC = 5,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+ SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+ SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+ SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+ SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+ SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+ SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+ SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+ SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+ SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+ SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+};
+
enum slpc_global_state {
SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
SLPC_GLOBAL_STATE_INITIALIZING = 1,
@@ -169,5 +192,12 @@ void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
void intel_slpc_suspend(struct drm_i915_private *dev_priv);
void intel_slpc_disable(struct drm_i915_private *dev_priv);
void intel_slpc_enable(struct drm_i915_private *dev_priv);
-
+void intel_slpc_unset_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id);
+void intel_slpc_set_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ u32 value);
+void intel_slpc_get_param(struct drm_i915_private *dev_priv,
+ enum slpc_param_id id,
+ int *overriding, u32 *value);
#endif
--
1.9.1
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