From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1.
Interpretation of default value is based on HAS_SLPC(), after
slpc_version_check(). This function also enforces the requirement
that guc_submission is required for slpc.
intel_slpc_enabled() returns 1 if SLPC should be used.
v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
Remove sanitize enable_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as
part of slpc_enable_sanitize function in the next patch. (Sagar)
Updated slpc option sanitize function call for platforms without
GuC support. This was caught by CI BAT.
v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.
v3: Rebase.
v4: Moved sanitization of SLPC option post GuC load.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_params.c | 6 ++++++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc.h | 7 +++++++
drivers/gpu/drm/i915/intel_guc_loader.c | 19 +++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 2 ++
5 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 768ad89..72b3097 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+ .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -131,6 +132,11 @@ MODULE_PARM_DESC(enable_execlists,
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
+module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400);
+MODULE_PARM_DESC(enable_slpc,
+ "Override single-loop-power-controller (slpc) usage. "
+ "(-1=auto, 0=disabled [default], 1=enabled)");
+
module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600);
MODULE_PARM_DESC(enable_psr, "Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3a0dd78..391c471 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -39,6 +39,7 @@ struct i915_params {
int enable_fbc;
int enable_ppgtt;
int enable_execlists;
+ int enable_slpc;
int enable_psr;
unsigned int preliminary_hw_support;
int disable_power_well;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 9e6b948..d73e4ed 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -146,6 +146,12 @@ struct intel_guc {
uint32_t last_seqno[I915_NUM_ENGINES];
};
+static inline int intel_slpc_enabled(void)
+{
+ WARN_ON(i915.enable_slpc < 0);
+ return i915.enable_slpc;
+}
+
/* intel_guc_loader.c */
extern void intel_guc_init(struct drm_device *dev);
extern int intel_guc_setup(struct drm_device *dev);
@@ -153,6 +159,7 @@ extern void intel_guc_fini(struct drm_device *dev);
extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
extern int intel_guc_suspend(struct drm_device *dev);
extern int intel_guc_resume(struct drm_device *dev);
+extern void sanitize_slpc_option(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 853928f..fb38018 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -144,6 +144,25 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
}
}
+void sanitize_slpc_option(struct drm_i915_private *dev_priv)
+{
+ /* Handle default case */
+ if (i915.enable_slpc < 0)
+ i915.enable_slpc = HAS_SLPC(dev_priv);
+
+ /* slpc requires hardware support and compatible firmware */
+ if (!HAS_SLPC(dev_priv))
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc loaded */
+ if (!i915.enable_guc_loading)
+ i915.enable_slpc = 0;
+
+ /* slpc requires guc submission */
+ if (!i915.enable_guc_submission)
+ i915.enable_slpc = 0;
+}
+
static u32 get_gttype(struct drm_i915_private *dev_priv)
{
/* XXX: GT type based on PCI device ID? field seems unused by fw */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b9c460c..56bde62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6598,6 +6598,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_runtime_pm_get(dev_priv);
}
+ sanitize_slpc_option(dev_priv);
+
mutex_lock(&dev_priv->drm.struct_mutex);
mutex_lock(&dev_priv->rps.hw_lock);
--
1.9.1
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