On Thu, 08 Sep 2016, Manasi Navare <manasi.d.navare@xxxxxxxxx> wrote:
> From: Durgadoss R <durgadoss.r@xxxxxxxxx>
>
> To support USB type C alternate DP mode, the display driver needs to
> know the number of lanes required by the DP panel as well as number
> of lanes that can be supported by the type-C cable. Sometimes, the
> type-C cable may limit the bandwidth even if Panel can support
> more lanes. To address these scenarios, the display driver will
> start link training with max lanes, and if that fails, the driver
> falls back to x2 lanes; and repeats this procedure for all
> bandwidth/lane configurations.
>
> * Since link training is done before modeset only the port
> (and not pipe/planes) and its associated PLLs are enabled.
> * On DP hotplug: Directly start link training on the DP encoder.
> * On Connected boot scenarios: When booted with an LFP and a DP,
> sometimes BIOS brings up DP. In these cases, we disable the
> crtc and then do upfront link training; and bring it back up.
> * All local changes made for upfront link training are reset
> to their previous values once it is done; so that the
> subsequent modeset is not aware of these changes.
As I said for a previous version, this needs to be split to functional
and non-functional parts.
> @@ -5618,6 +5794,13 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> if (type == DRM_MODE_CONNECTOR_eDP)
> intel_encoder->type = INTEL_OUTPUT_EDP;
>
> + /* Initialize upfront link training vfunc for DP */
> + if (intel_encoder->type != INTEL_OUTPUT_EDP) {
> + if (IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv) ||
> + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
What's this based on? What happened to Kabylake?
> + intel_dp->upfront_link_train = intel_ddi_link_train;
> + }
> +
> /* eDP only on port B and/or C on vlv/chv */
> if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
> is_edp(intel_dp) && port != PORT_B && port != PORT_C))
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index f1e08f0..b6f380b 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -304,7 +304,6 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
> intel_dp_set_idle_link_train(intel_dp);
>
> return intel_dp->channel_eq_status;
> -
> }
>
> void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5b97a7d4..e5ab375 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -882,6 +882,12 @@ struct intel_dp {
> enum hdmi_force_audio force_audio;
> bool limited_color_range;
> bool color_range_auto;
> +
> + /* Upfront link train parameters */
> + int max_link_rate_upfront;
> + uint8_t max_lanes_upfront;
> + bool upfront_done;
> +
> uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> @@ -939,6 +945,11 @@ struct intel_dp {
> /* This is called before a link training is starterd */
> void (*prepare_link_retrain)(struct intel_dp *intel_dp);
>
> + /* For Upfront link training */
> + bool (*upfront_link_train)(struct intel_dp *intel_dp, int clock,
> + uint8_t lane_count, bool link_mst,
> + bool is_upfront);
> +
> /* Displayport compliance testing */
> unsigned long compliance_test_type;
> unsigned long compliance_test_data;
> @@ -1161,7 +1172,8 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
> void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> bool intel_ddi_link_train(struct intel_dp *intel_dp, int max_link_rate,
> - uint8_t max_lane_count, bool link_mst);
> + uint8_t max_lane_count, bool link_mst,
> + bool is_upfront);
> struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
> int clock);
> unsigned int intel_fb_align_height(struct drm_device *dev,
--
Jani Nikula, Intel Open Source Technology Center
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