On Tue, Sep 06, 2016 at 10:40:17AM +0300, Joonas Lahtinen wrote: > On ti, 2016-09-06 at 07:19 +0100, Chris Wilson wrote: > > @@ -3725,7 +3723,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); > > * act upon the intermediate value, possibly leading to corruption and > > * machine death. You have been warned. > > */ > > I'd update the comment, it's about interpreting the intermediate value > now. And maybe explicitly state that we do not do 64-bit writes. I glanced over it, the warning about the hw acting upon the intermdiate value still seemed appropriate (even without us having a WRITE64). All that it is missing is the extra warning that we do not support writeq via the vfunc. /* Be very careful with read/write 64-bit values. On 32-bit machines, they * will be implemented using 2 32-bit writes in an arbitrary order with * an arbitrary delay between them. This can cause the hardware to * act upon the intermediate value, possibly leading to corruption and * machine death. For this reason we do not support I915_WRITE64, or * dev_priv->uncore.funcs.mmio_writeq. * * When reading a 64-bit value as two 32-bit values, the delay may cause * the two reads to mismatch, e.g. a timestamp overflowing. Also note that * occasionally a 64-bit register does not actualy support a full readq * and must be read using two 32-bit reads. * * You have been warned. */ -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
