On Thu, 2016-08-04 at 04:07 +0100, Chris Wilson wrote: > On Wed, Aug 03, 2016 at 08:07:38PM -0700, Dhinakaran Pandiyan wrote: > > @@ -2588,7 +2592,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > > break; > > case DP_TRAINING_PATTERN_3: > > - DRM_ERROR("DP training pattern 3 not supported\n"); > > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > > *DP |= DP_LINK_TRAIN_PAT_2_CPT; > > break; > > } > > @@ -2613,7 +2617,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, > > if (IS_CHERRYVIEW(dev)) { > > *DP |= DP_LINK_TRAIN_PAT_3_CHV; > > } else { > > - DRM_ERROR("DP training pattern 3 not supported\n"); > > + DRM_ERROR("TPS3 not supported, using TPS2 instead\n"); > > *DP |= DP_LINK_TRAIN_PAT_2; > > Given that you have a fallback plan and if the fallback plan fails you > alert the user with an error already, these aren't errors but debug. > -Chris > I will make that change. Thanks for the review. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx