On Tue, Aug 02, 2016 at 11:15:27AM +0100, Chris Wilson wrote:
> In the middle of intel_gt_init_powersave() we have an if-chain that ends
> with a universal else clause to read gen6+ registers. Older platforms
> like Pineview that end up here do not like those registers and may even
> OOPS whilst reading them!
>
> Fixes: 3a45b05c4517 ("drm/i915: Preserve current RPS frequency across init")
Shouldn't that be
Fixes: 773ea9a80132 ("drm/i915: Perform static RPS frequency setup before userspace") ?
Either way,
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1ac32428d4db..86e136c23ac2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6493,7 +6493,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
> cherryview_init_gt_powersave(dev_priv);
> else if (IS_VALLEYVIEW(dev_priv))
> valleyview_init_gt_powersave(dev_priv);
> - else
> + else if (INTEL_GEN(dev_priv) >= 6)
> gen6_init_rps_frequencies(dev_priv);
>
> /* Derive initial user preferences/limits from the hardware limits */
> --
> 2.8.1
--
Ville Syrjälä
Intel OTC
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