This is completely untested (and probably horribly broken/buggy), but
here's a quick mockup of the general approach I was thinking for
ensuring DDB & WM's can be updated together while ensuring the
three-step pipe flushing process is honored:
https://github.com/mattrope/kernel/commits/experimental/lyude_ddb
Basically the idea is to take note of what's happening to the pipe's DDB
allocation (shrinking, growing, unchanged, etc.) during the atomic check
phase; then during the commit phase, we loop over the CRTC's three times
instead of just once, but only operate on a subset of the CRTC's in each
loop. While operating on each CRTC, the plane, WM, and DDB all get
programmed together and have a single flush for all three.
Matt
On Tue, Jul 26, 2016 at 01:34:36PM -0400, Lyude wrote:
> Latest version of https://lkml.org/lkml/2016/7/26/290 . Resending the whole
> thing to keep it in one place.
>
> Lyude (5):
> drm/i915/skl: Add support for the SAGV, fix underrun hangs
> drm/i915/skl: Only flush pipes when we change the ddb allocation
> drm/i915/skl: Fix extra whitespace in skl_flush_wm_values()
> drm/i915/skl: Update plane watermarks atomically during plane updates
> drm/i915/skl: Always wait for pipes to update after a flush
>
> Matt Roper (1):
> drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/intel_display.c | 24 ++++
> drivers/gpu/drm/i915/intel_drv.h | 4 +
> drivers/gpu/drm/i915/intel_pm.c | 240 +++++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_sprite.c | 2 +
> 6 files changed, 255 insertions(+), 23 deletions(-)
>
> --
> 2.7.4
>
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--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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