On Wed, Jun 29, 2016 at 12:38:51PM +0100, Chris Wilson wrote:
> Several years ago we made the plan of only having one canonical source
> for i915_pciids.h, the kernel and everyone importing their definitions
> from that. For consistency, we style the intel_device_info after the
> kernel, most notably using a generation mask and a per-codename bitfield.
>
> This first step converts looking up the generation for a devid tree from
> a massive if(devid)-chain to a (cached) table lookup.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Should we extract the kernels list of chipset into intel_chipset.c too, to
make them 1:1 copies like with i915_pciids.h? With that this (entire
series) here has my ack. Without I'm not sold that much on the churn
really.
-Daniel
> ---
> lib/Makefile.sources | 3 +-
> lib/drmtest.c | 2 +-
> lib/i915_pciids.h | 132 +++++++++++++++++-
> lib/intel_chipset.c | 31 -----
> lib/intel_chipset.h | 116 +++++++---------
> lib/intel_device_info.c | 288 ++++++++++++++++++++++++++++++++++++++
> overlay/i915_pciids.h | 339 ---------------------------------------------
> overlay/igfx.c | 2 +-
> tools/intel_audio_dump.c | 12 +-
> tools/intel_error_decode.c | 2 +-
> tools/intel_reg.c | 21 +--
> 11 files changed, 476 insertions(+), 472 deletions(-)
> create mode 100644 lib/intel_device_info.c
> delete mode 100644 overlay/i915_pciids.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 3589e26..8cad9d5 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -26,11 +26,12 @@ libintel_tools_la_SOURCES = \
> instdone.h \
> intel_batchbuffer.c \
> intel_batchbuffer.h \
> + intel_chipset.c \
> intel_chipset.h \
> + intel_device_info.c \
> intel_os.c \
> intel_io.h \
> intel_mmio.c \
> - intel_chipset.c \
> intel_reg.h \
> ioctl_wrappers.c \
> ioctl_wrappers.h \
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 884fe7c..62dd042 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -127,7 +127,7 @@ static bool has_known_intel_chipset(int fd)
> if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp)))
> return false;
>
> - if (!IS_INTEL(devid))
> + if (!intel_gen(devid))
> return false;
>
> __drm_device_id = devid;
> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> index 8a10f5c..33466bf 100644
> --- a/lib/i915_pciids.h
> +++ b/lib/i915_pciids.h
> @@ -191,8 +191,8 @@
> INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
> + INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> + INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> @@ -208,4 +208,132 @@
> #define INTEL_VLV_D_IDS(info) \
> INTEL_VGA_DEVICE(0x0155, info)
>
> +#define INTEL_BDW_GT12M_IDS(info) \
> + INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> + INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> + INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> + INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> + INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> + INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> + INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> + INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> +
> +#define INTEL_BDW_GT12D_IDS(info) \
> + INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> + INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
> + INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> + INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> +
> +#define INTEL_BDW_GT3M_IDS(info) \
> + INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> + INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> +
> +#define INTEL_BDW_GT3D_IDS(info) \
> + INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> + INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> +
> +#define INTEL_BDW_RSVDM_IDS(info) \
> + INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> + INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
> + INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> +
> +#define INTEL_BDW_RSVDD_IDS(info) \
> + INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> + INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> +
> +#define INTEL_BDW_M_IDS(info) \
> + INTEL_BDW_GT12M_IDS(info), \
> + INTEL_BDW_GT3M_IDS(info), \
> + INTEL_BDW_RSVDM_IDS(info)
> +
> +#define INTEL_BDW_D_IDS(info) \
> + INTEL_BDW_GT12D_IDS(info), \
> + INTEL_BDW_GT3D_IDS(info), \
> + INTEL_BDW_RSVDD_IDS(info)
> +
> +#define INTEL_CHV_IDS(info) \
> + INTEL_VGA_DEVICE(0x22b0, info), \
> + INTEL_VGA_DEVICE(0x22b1, info), \
> + INTEL_VGA_DEVICE(0x22b2, info), \
> + INTEL_VGA_DEVICE(0x22b3, info)
> +
> +#define INTEL_SKL_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> +
> +#define INTEL_SKL_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> + INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
> + INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
> + INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> + INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> +
> +#define INTEL_SKL_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> + INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
> +
> +#define INTEL_SKL_GT4_IDS(info) \
> + INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> + INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> + INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> + INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
> +
> +#define INTEL_SKL_IDS(info) \
> + INTEL_SKL_GT1_IDS(info), \
> + INTEL_SKL_GT2_IDS(info), \
> + INTEL_SKL_GT3_IDS(info), \
> + INTEL_SKL_GT4_IDS(info)
> +
> +#define INTEL_BXT_IDS(info) \
> + INTEL_VGA_DEVICE(0x0A84, info), \
> + INTEL_VGA_DEVICE(0x1A84, info), \
> + INTEL_VGA_DEVICE(0x1A85, info), \
> + INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> + INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> +
> +#define INTEL_KBL_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> + INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> + INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> + INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> + INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> + INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> +
> +#define INTEL_KBL_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> + INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> + INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> + INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> + INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> + INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> + INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> +
> +#define INTEL_KBL_GT3_IDS(info) \
> + INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
> + INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> +
> +#define INTEL_KBL_GT4_IDS(info) \
> + INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> +
> +#define INTEL_KBL_IDS(info) \
> + INTEL_KBL_GT1_IDS(info), \
> + INTEL_KBL_GT2_IDS(info), \
> + INTEL_KBL_GT3_IDS(info), \
> + INTEL_KBL_GT4_IDS(info)
> +
> #endif /* _I915_PCIIDS_H */
> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> index 56746b0..777dfa7 100644
> --- a/lib/intel_chipset.c
> +++ b/lib/intel_chipset.c
> @@ -141,37 +141,6 @@ intel_get_drm_devid(int fd)
> }
>
> /**
> - * intel_gen:
> - * @devid: pci device id
> - *
> - * Computes the Intel GFX generation for the give device id.
> - *
> - * Returns:
> - * The GFX generation on successful lookup, -1 on failure.
> - */
> -int intel_gen(uint32_t devid)
> -{
> - if (IS_GEN2(devid))
> - return 2;
> - if (IS_GEN3(devid))
> - return 3;
> - if (IS_GEN4(devid))
> - return 4;
> - if (IS_GEN5(devid))
> - return 5;
> - if (IS_GEN6(devid))
> - return 6;
> - if (IS_GEN7(devid))
> - return 7;
> - if (IS_GEN8(devid))
> - return 8;
> - if (IS_GEN9(devid))
> - return 9;
> -
> - return -1;
> -}
> -
> -/**
> * intel_check_pch:
> *
> * Detects the PCH chipset type of the running systems and fills in the results
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index e1e552c..69c878b 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -29,10 +29,44 @@
> #define _INTEL_CHIPSET_H
>
> #include <pciaccess.h>
> +#include <stdbool.h>
>
> struct pci_device *intel_get_pci_device(void);
> uint32_t intel_get_drm_devid(int fd);
> -int intel_gen(uint32_t devid);
> +
> +const struct intel_device_info {
> + unsigned gen;
> + bool is_mobile : 1;
> + bool is_whitney : 1;
> + bool is_almador : 1;
> + bool is_brookdale : 1;
> + bool is_montara : 1;
> + bool is_springdale : 1;
> + bool is_grantsdale : 1;
> + bool is_alviso : 1;
> + bool is_lakeport : 1;
> + bool is_calistoga : 1;
> + bool is_bearlake : 1;
> + bool is_pineview : 1;
> + bool is_broadwater : 1;
> + bool is_crestline : 1;
> + bool is_eaglelake : 1;
> + bool is_cantiga : 1;
> + bool is_ironlake : 1;
> + bool is_arrandale : 1;
> + bool is_sandybridge : 1;
> + bool is_ivybridge : 1;
> + bool is_valleyview : 1;
> + bool is_haswell : 1;
> + bool is_broadwell : 1;
> + bool is_cherryview : 1;
> + bool is_skylake : 1;
> + bool is_broxton : 1;
> + bool is_kabylake : 1;
> + const char *codename;
> +} *intel_device_info(uint16_t devid) __attribute__((pure));
> +
> +unsigned intel_gen(uint16_t devid) __attribute__((pure));
>
> extern enum pch_type intel_pch;
>
> @@ -275,36 +309,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_Q33_G || \
> (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
>
> -#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
> - (devid) == PCI_CHIP_845_G || \
> - (devid) == PCI_CHIP_I854_G || \
> - (devid) == PCI_CHIP_I855_GM || \
> - (devid) == PCI_CHIP_I865_G)
> -
> -#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
> -
> -#define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
> - (devid) == PCI_CHIP_I965_Q || \
> - (devid) == PCI_CHIP_I965_G_1 || \
> - (devid) == PCI_CHIP_I965_GM || \
> - (devid) == PCI_CHIP_I965_GME || \
> - (devid) == PCI_CHIP_I946_GZ || \
> - IS_G4X(devid))
> -
> -#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
> -
> -#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
> - (devid) == PCI_CHIP_SANDYBRIDGE_S)
> -
> -#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
> - IS_HASWELL(devid) || \
> - IS_VALLEYVIEW(devid))
> -
> #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
> (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
> (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
> @@ -396,9 +400,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_CHERRYVIEW_2 || \
> (devid) == PCI_CHIP_CHERRYVIEW_3)
>
> -#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
> - IS_CHERRYVIEW(devid))
> -
> #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
> (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
> (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
> @@ -462,10 +463,6 @@ void intel_check_pch(void);
> (devid) == PCI_CHIP_BROXTON_3 || \
> (devid) == PCI_CHIP_BROXTON_4)
>
> -#define IS_GEN9(devid) (IS_KABYLAKE(devid) || \
> - IS_SKYLAKE(devid) || \
> - IS_BROXTON(devid))
> -
> #define IS_965(devid) (IS_GEN4(devid) || \
> IS_GEN5(devid) || \
> IS_GEN6(devid) || \
> @@ -473,32 +470,6 @@ void intel_check_pch(void);
> IS_GEN8(devid) || \
> IS_GEN9(devid))
>
> -#define IS_INTEL(devid) (IS_GEN2(devid) || \
> - IS_GEN3(devid) || \
> - IS_GEN4(devid) || \
> - IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> -#define HAS_PCH_SPLIT(devid) (IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_IVYBRIDGE(devid) || IS_HASWELL(devid) || \
> - IS_BROADWELL(devid) || \
> - IS_SKYLAKE(devid))
> -
> -#define HAS_BLT_RING(devid) (IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> -#define HAS_BSD_RING(devid) (IS_GEN5(devid) || \
> - IS_GEN6(devid) || \
> - IS_GEN7(devid) || \
> - IS_GEN8(devid) || \
> - IS_GEN9(devid))
> -
> #define IS_BROADWATER(devid) ((devid) == PCI_CHIP_I946_GZ || \
> (devid) == PCI_CHIP_I965_G_1 || \
> (devid) == PCI_CHIP_I965_Q || \
> @@ -507,6 +478,21 @@ void intel_check_pch(void);
> #define IS_CRESTLINE(devid) ((devid) == PCI_CHIP_I965_GM || \
> (devid) == PCI_CHIP_I965_GME)
>
> -#define HAS_VEBOX_RING(devid) (IS_HASWELL(devid))
> +#define IS_GEN(devid, x) (intel_device_info(devid)->gen & (1u << ((x)-1)))
> +#define AT_LEAST_GEN(devid, x) (intel_device_info(devid)->gen & -(1u << ((x)-1)))
> +
> +#define IS_GEN2(devid) IS_GEN(devid, 2)
> +#define IS_GEN3(devid) IS_GEN(devid, 3)
> +#define IS_GEN4(devid) IS_GEN(devid, 4)
> +#define IS_GEN5(devid) IS_GEN(devid, 5)
> +#define IS_GEN6(devid) IS_GEN(devid, 6)
> +#define IS_GEN7(devid) IS_GEN(devid, 7)
> +#define IS_GEN8(devid) IS_GEN(devid, 8)
> +#define IS_GEN9(devid) IS_GEN(devid, 9)
> +
> +#define HAS_BSD_RING(devid) AT_LEAST_GEN(devid, 5)
> +#define HAS_BLT_RING(devid) AT_LEAST_GEN(devid, 6)
> +
> +#define HAS_PCH_SPLIT(devid) AT_LEAST_GEN(devid, 5) /* XXX Valleyview? */
>
> #endif /* _INTEL_CHIPSET_H */
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> new file mode 100644
> index 0000000..7e26406
> --- /dev/null
> +++ b/lib/intel_device_info.c
> @@ -0,0 +1,288 @@
> +#include "intel_chipset.h"
> +#include "i915_pciids.h"
> +
> +#include <strings.h> /* ffs() */
> +
> +#define BIT(x) (1<<(x))
> +
> +static const struct intel_device_info intel_generic_info = {
> + .gen = 0,
> +};
> +
> +static const struct intel_device_info intel_i81x_info = {
> + .gen = BIT(0),
> + .is_whitney = true,
> + .codename = "solano/whitney"
> +};
> +
> +static const struct intel_device_info intel_i830_info = {
> + .gen = BIT(1),
> + .is_almador = true,
> + .codename = "almador"
> +};
> +static const struct intel_device_info intel_i845_info = {
> + .gen = BIT(1),
> + .is_brookdale = true,
> + .codename = "brookdale"
> +};
> +static const struct intel_device_info intel_i855_info = {
> + .gen = BIT(1),
> + .is_mobile = true,
> + .is_montara = true,
> + .codename = "montara"
> +};
> +static const struct intel_device_info intel_i865_info = {
> + .gen = BIT(1),
> + .is_springdale = true,
> + .codename = "spingdale"
> +};
> +
> +static const struct intel_device_info intel_i915_info = {
> + .gen = BIT(2),
> + .is_grantsdale = true,
> + .codename = "grantsdale"
> +};
> +static const struct intel_device_info intel_i915m_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_alviso = true,
> + .codename = "alviso"
> +};
> +static const struct intel_device_info intel_i945_info = {
> + .gen = BIT(2),
> + .is_lakeport = true,
> + .codename = "lakeport"
> +};
> +static const struct intel_device_info intel_i945m_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_calistoga = true,
> + .codename = "calistoga"
> +};
> +
> +static const struct intel_device_info intel_g33_info = {
> + .gen = BIT(2),
> + .is_bearlake = true,
> + .codename = "bearlake"
> +};
> +static const struct intel_device_info intel_pineview_info = {
> + .gen = BIT(2),
> + .is_mobile = true,
> + .is_pineview = true,
> + .codename = "pineview"
> +};
> +
> +static const struct intel_device_info intel_i965_info = {
> + .gen = BIT(3),
> + .is_broadwater = true,
> + .codename = "broadwater"
> +};
> +
> +static const struct intel_device_info intel_i965m_info = {
> + .gen = BIT(3),
> + .is_mobile = true,
> + .is_crestline = true,
> + .codename = "crestline"
> +};
> +
> +static const struct intel_device_info intel_g45_info = {
> + .gen = BIT(3),
> + .is_eaglelake = true,
> + .codename = "aaglelake"
> +};
> +static const struct intel_device_info intel_gm45_info = {
> + .gen = BIT(3),
> + .is_mobile = true,
> + .is_cantiga = true,
> + .codename = "cantiga"
> +};
> +
> +static const struct intel_device_info intel_ironlake_info = {
> + .gen = BIT(4),
> + .is_ironlake = true,
> + .codename = "ironlake"
> +};
> +static const struct intel_device_info intel_ironlake_m_info = {
> + .gen = BIT(4),
> + .is_mobile = true,
> + .is_arrandale = true,
> + .codename = "arrandale"
> +};
> +
> +static const struct intel_device_info intel_sandybridge_info = {
> + .gen = BIT(5),
> + .is_sandybridge = true,
> + .codename = "sandybridge"
> +};
> +static const struct intel_device_info intel_sandybridge_m_info = {
> + .gen = BIT(5),
> + .is_mobile = true,
> + .is_sandybridge = true,
> + .codename = "sandybridge"
> +};
> +
> +static const struct intel_device_info intel_ivybridge_info = {
> + .gen = BIT(6),
> + .is_ivybridge = true,
> + .codename = "ivybridge"
> +};
> +static const struct intel_device_info intel_ivybridge_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_ivybridge = true,
> + .codename = "ivybridge"
> +};
> +
> +static const struct intel_device_info intel_valleyview_info = {
> + .gen = BIT(6),
> + .is_valleyview = true,
> + .codename = "valleyview"
> +};
> +static const struct intel_device_info intel_valleyview_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_valleyview = true,
> + .codename = "valleyview"
> +};
> +
> +static const struct intel_device_info intel_haswell_info = {
> + .gen = BIT(6),
> + .is_haswell = true,
> + .codename = "haswell"
> +};
> +static const struct intel_device_info intel_haswell_m_info = {
> + .gen = BIT(6),
> + .is_mobile = true,
> + .is_haswell = true,
> + .codename = "haswell"
> +};
> +
> +static const struct intel_device_info intel_broadwell_info = {
> + .gen = BIT(7),
> + .is_broadwell = true,
> + .codename = "broadwell"
> +};
> +static const struct intel_device_info intel_broadwell_m_info = {
> + .gen = BIT(7),
> + .is_mobile = true,
> + .is_broadwell = true,
> + .codename = "broadwell"
> +};
> +
> +static const struct intel_device_info intel_cherryview_info = {
> + .gen = BIT(7),
> + .is_cherryview = true,
> + .codename = "cherryview"
> +};
> +
> +static const struct intel_device_info intel_skylake_info = {
> + .gen = BIT(8),
> + .is_skylake = true,
> + .codename = "skylake"
> +};
> +
> +static const struct intel_device_info intel_broxton_info = {
> + .gen = BIT(8),
> + .is_broxton = true,
> + .codename = "broxton"
> +};
> +
> +static const struct intel_device_info intel_kabylake_info = {
> + .gen = BIT(8),
> + .is_kabylake = true,
> + .codename = "kabylake"
> +};
> +
> +static const struct pci_id_match intel_device_match[] = {
> + INTEL_I830_IDS(&intel_i830_info),
> + INTEL_I845G_IDS(&intel_i845_info),
> + INTEL_I85X_IDS(&intel_i855_info),
> + INTEL_I865G_IDS(&intel_i865_info),
> +
> + INTEL_I915G_IDS(&intel_i915_info),
> + INTEL_I915GM_IDS(&intel_i915m_info),
> + INTEL_I945G_IDS(&intel_i945_info),
> + INTEL_I945GM_IDS(&intel_i945m_info),
> +
> + INTEL_G33_IDS(&intel_g33_info),
> + INTEL_PINEVIEW_IDS(&intel_pineview_info),
> +
> + INTEL_I965G_IDS(&intel_i965_info),
> + INTEL_I965GM_IDS(&intel_i965_info),
> +
> + INTEL_G45_IDS(&intel_g45_info),
> + INTEL_GM45_IDS(&intel_gm45_info),
> +
> + INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
> + INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
> +
> + INTEL_SNB_D_IDS(&intel_sandybridge_info),
> + INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
> +
> + INTEL_IVB_D_IDS(&intel_ivybridge_info),
> + INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
> +
> + INTEL_HSW_D_IDS(&intel_haswell_info),
> + INTEL_HSW_M_IDS(&intel_haswell_m_info),
> +
> + INTEL_VLV_D_IDS(&intel_valleyview_info),
> + INTEL_VLV_M_IDS(&intel_valleyview_m_info),
> +
> + INTEL_BDW_D_IDS(&intel_broadwell_info),
> + INTEL_BDW_M_IDS(&intel_broadwell_m_info),
> +
> + INTEL_CHV_IDS(&intel_cherryview_info),
> +
> + INTEL_SKL_IDS(&intel_skylake_info),
> +
> + INTEL_BXT_IDS(&intel_broxton_info),
> +
> + INTEL_KBL_IDS(&intel_kabylake_info),
> +
> + INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> +};
> +
> +/**
> + * intel_device_info:
> + * @devid: pci device id
> + *
> + * Looks up the Intel GFX device info for the given device id.
> + *
> + * Returns:
> + * The associated intel_device_info
> + */
> +const struct intel_device_info *intel_device_info(uint16_t devid)
> +{
> + static const struct intel_device_info *cache = &intel_generic_info;
> + static uint16_t cached_devid;
> + int i;
> +
> + if (cached_devid == devid)
> + goto out;
> +
> + /* XXX Presort table and bsearch! */
> + for (i = 0; intel_device_match[i].device_id != PCI_MATCH_ANY; i++) {
> + if (devid == intel_device_match[i].device_id)
> + break;
> + }
> +
> + cached_devid = devid;
> + cache = (void *)intel_device_match[i].match_data;
> +
> +out:
> + return cache;
> +}
> +
> +/**
> + * intel_gen:
> + * @devid: pci device id
> + *
> + * Computes the Intel GFX generation for the given device id.
> + *
> + * Returns:
> + * The GFX generation on successful lookup, 0 on failure.
> + */
> +unsigned intel_gen(uint16_t devid)
> +{
> + return ffs(intel_device_info(devid)->gen);
> +}
> diff --git a/overlay/i915_pciids.h b/overlay/i915_pciids.h
> deleted file mode 100644
> index 33466bf..0000000
> --- a/overlay/i915_pciids.h
> +++ /dev/null
> @@ -1,339 +0,0 @@
> -/*
> - * Copyright 2013 Intel Corporation
> - * All Rights Reserved.
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a
> - * copy of this software and associated documentation files (the
> - * "Software"), to deal in the Software without restriction, including
> - * without limitation the rights to use, copy, modify, merge, publish,
> - * distribute, sub license, and/or sell copies of the Software, and to
> - * permit persons to whom the Software is furnished to do so, subject to
> - * the following conditions:
> - *
> - * The above copyright notice and this permission notice (including the
> - * next paragraph) shall be included in all copies or substantial portions
> - * of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> - * DEALINGS IN THE SOFTWARE.
> - */
> -#ifndef _I915_PCIIDS_H
> -#define _I915_PCIIDS_H
> -
> -/*
> - * A pci_device_id struct {
> - * __u32 vendor, device;
> - * __u32 subvendor, subdevice;
> - * __u32 class, class_mask;
> - * kernel_ulong_t driver_data;
> - * };
> - * Don't use C99 here because "class" is reserved and we want to
> - * give userspace flexibility.
> - */
> -#define INTEL_VGA_DEVICE(id, info) { \
> - 0x8086, id, \
> - ~0, ~0, \
> - 0x030000, 0xff0000, \
> - (unsigned long) info }
> -
> -#define INTEL_QUANTA_VGA_DEVICE(info) { \
> - 0x8086, 0x16a, \
> - 0x152d, 0x8990, \
> - 0x030000, 0xff0000, \
> - (unsigned long) info }
> -
> -#define INTEL_I830_IDS(info) \
> - INTEL_VGA_DEVICE(0x3577, info)
> -
> -#define INTEL_I845G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2562, info)
> -
> -#define INTEL_I85X_IDS(info) \
> - INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
> - INTEL_VGA_DEVICE(0x358e, info)
> -
> -#define INTEL_I865G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
> -
> -#define INTEL_I915G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
> - INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
> -
> -#define INTEL_I915GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
> -
> -#define INTEL_I945G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
> -
> -#define INTEL_I945GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
> - INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
> -
> -#define INTEL_I965G_IDS(info) \
> - INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
> - INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
> - INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
> - INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
> -
> -#define INTEL_G33_IDS(info) \
> - INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
> - INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
> - INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
> -
> -#define INTEL_I965GM_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
> - INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
> -
> -#define INTEL_GM45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
> -
> -#define INTEL_G45_IDS(info) \
> - INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
> - INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
> - INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
> - INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
> - INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> - INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
> -
> -#define INTEL_PINEVIEW_IDS(info) \
> - INTEL_VGA_DEVICE(0xa001, info), \
> - INTEL_VGA_DEVICE(0xa011, info)
> -
> -#define INTEL_IRONLAKE_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0042, info)
> -
> -#define INTEL_IRONLAKE_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0046, info)
> -
> -#define INTEL_SNB_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0102, info), \
> - INTEL_VGA_DEVICE(0x0112, info), \
> - INTEL_VGA_DEVICE(0x0122, info), \
> - INTEL_VGA_DEVICE(0x010A, info)
> -
> -#define INTEL_SNB_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0106, info), \
> - INTEL_VGA_DEVICE(0x0116, info), \
> - INTEL_VGA_DEVICE(0x0126, info)
> -
> -#define INTEL_IVB_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
> -
> -#define INTEL_IVB_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
> -
> -#define INTEL_IVB_Q_IDS(info) \
> - INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
> -
> -#define INTEL_HSW_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
> - INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
> - INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
> - INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> - INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> - INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> - INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
> -
> -#define INTEL_HSW_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> -
> -#define INTEL_VLV_M_IDS(info) \
> - INTEL_VGA_DEVICE(0x0f30, info), \
> - INTEL_VGA_DEVICE(0x0f31, info), \
> - INTEL_VGA_DEVICE(0x0f32, info), \
> - INTEL_VGA_DEVICE(0x0f33, info), \
> - INTEL_VGA_DEVICE(0x0157, info)
> -
> -#define INTEL_VLV_D_IDS(info) \
> - INTEL_VGA_DEVICE(0x0155, info)
> -
> -#define INTEL_BDW_GT12M_IDS(info) \
> - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \
> - INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \
> - INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \
> - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \
> - INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \
> - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */
> -
> -#define INTEL_BDW_GT12D_IDS(info) \
> - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \
> - INTEL_VGA_DEVICE(0x160D, info), /* GT1 Workstation */ \
> - INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \
> - INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */
> -
> -#define INTEL_BDW_GT3M_IDS(info) \
> - INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \
> - INTEL_VGA_DEVICE(0x162E, info) /* ULX */
> -
> -#define INTEL_BDW_GT3D_IDS(info) \
> - INTEL_VGA_DEVICE(0x162A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x162D, info) /* Workstation */
> -
> -#define INTEL_BDW_RSVDM_IDS(info) \
> - INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \
> - INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \
> - INTEL_VGA_DEVICE(0x163E, info) /* ULX */
> -
> -#define INTEL_BDW_RSVDD_IDS(info) \
> - INTEL_VGA_DEVICE(0x163A, info), /* Server */ \
> - INTEL_VGA_DEVICE(0x163D, info) /* Workstation */
> -
> -#define INTEL_BDW_M_IDS(info) \
> - INTEL_BDW_GT12M_IDS(info), \
> - INTEL_BDW_GT3M_IDS(info), \
> - INTEL_BDW_RSVDM_IDS(info)
> -
> -#define INTEL_BDW_D_IDS(info) \
> - INTEL_BDW_GT12D_IDS(info), \
> - INTEL_BDW_GT3D_IDS(info), \
> - INTEL_BDW_RSVDD_IDS(info)
> -
> -#define INTEL_CHV_IDS(info) \
> - INTEL_VGA_DEVICE(0x22b0, info), \
> - INTEL_VGA_DEVICE(0x22b1, info), \
> - INTEL_VGA_DEVICE(0x22b2, info), \
> - INTEL_VGA_DEVICE(0x22b3, info)
> -
> -#define INTEL_SKL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */
> -
> -#define INTEL_SKL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
> - INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
> -
> -#define INTEL_SKL_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
> - INTEL_VGA_DEVICE(0x192A, info) /* SRV GT3 */
> -
> -#define INTEL_SKL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \
> - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \
> - INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \
> - INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4 */
> -
> -#define INTEL_SKL_IDS(info) \
> - INTEL_SKL_GT1_IDS(info), \
> - INTEL_SKL_GT2_IDS(info), \
> - INTEL_SKL_GT3_IDS(info), \
> - INTEL_SKL_GT4_IDS(info)
> -
> -#define INTEL_BXT_IDS(info) \
> - INTEL_VGA_DEVICE(0x0A84, info), \
> - INTEL_VGA_DEVICE(0x1A84, info), \
> - INTEL_VGA_DEVICE(0x1A85, info), \
> - INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \
> - INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */
> -
> -#define INTEL_KBL_GT1_IDS(info) \
> - INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5917, info), /* DT GT1.5 */ \
> - INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
> - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
> - INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
> - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
> - INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
> -
> -#define INTEL_KBL_GT2_IDS(info) \
> - INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \
> - INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \
> - INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \
> - INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \
> - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \
> - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \
> - INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
> -
> -#define INTEL_KBL_GT3_IDS(info) \
> - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
> - INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
> -
> -#define INTEL_KBL_GT4_IDS(info) \
> - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
> -
> -#define INTEL_KBL_IDS(info) \
> - INTEL_KBL_GT1_IDS(info), \
> - INTEL_KBL_GT2_IDS(info), \
> - INTEL_KBL_GT3_IDS(info), \
> - INTEL_KBL_GT4_IDS(info)
> -
> -#endif /* _I915_PCIIDS_H */
> diff --git a/overlay/igfx.c b/overlay/igfx.c
> index 604ae5f..fa046e7 100644
> --- a/overlay/igfx.c
> +++ b/overlay/igfx.c
> @@ -29,7 +29,7 @@
> #include <stdio.h>
>
> #include "igfx.h"
> -#include "i915_pciids.h"
> +#include "../lib/i915_pciids.h"
>
> static const struct igfx_info generic_info = {
> .gen = -1,
> diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
> index aec4177..aacd52f 100644
> --- a/tools/intel_audio_dump.c
> +++ b/tools/intel_audio_dump.c
> @@ -2476,31 +2476,21 @@ int main(int argc, char **argv)
> else
> intel_mmio_use_pci_bar(pci_dev);
>
> + printf("%s audio registers:\n\n", intel_device_info(devid)->codename);
> if (IS_VALLEYVIEW(devid)) {
> - printf("Valleyview audio registers:\n\n");
> dump_ironlake();
> } else if (IS_GEN9(devid)
> || IS_BROADWELL(devid) || IS_HASWELL(devid)) {
> - printf("%s audio registers:\n\n",
> - IS_BROXTON(devid) ? "Broxton" :
> - (IS_KABYLAKE(devid) ? "Kabylake" :
> - (IS_SKYLAKE(devid) ? "Skylake" :
> - (IS_BROADWELL(devid) ? "Broadwell" : "Haswell"))));
> dump_hsw_plus();
> } else if (IS_GEN6(devid) || IS_GEN7(devid)
> || getenv("HAS_PCH_SPLIT")) {
> - printf("%s audio registers:\n\n",
> - IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
> intel_check_pch();
> dump_cpt();
> } else if (IS_GEN5(devid)) {
> - printf("Ironlake audio registers:\n\n");
> dump_ironlake();
> } else if (IS_G4X(devid)) {
> - printf("G45 audio registers:\n\n");
> dump_eaglelake();
> } else if (IS_CHERRYVIEW(devid)) {
> - printf("Braswell audio registers:\n\n");
> dump_braswell();
> }
>
> diff --git a/tools/intel_error_decode.c b/tools/intel_error_decode.c
> index 371aa42..7959fff 100644
> --- a/tools/intel_error_decode.c
> +++ b/tools/intel_error_decode.c
> @@ -847,4 +847,4 @@ main(int argc, char *argv[])
> return 0;
> }
>
> -/* vim: set ts=8 sw=8 tw=0 noet :*/
> +/* vim: set ts=8 sw=8 tw=0 cino=:0,(0 noet :*/
> diff --git a/tools/intel_reg.c b/tools/intel_reg.c
> index 92be1ce..73fbd6d 100644
> --- a/tools/intel_reg.c
> +++ b/tools/intel_reg.c
> @@ -657,26 +657,7 @@ static int intel_reg_help(struct config *config, int argc, char *argv[])
> */
> static const char *get_codename(uint32_t devid)
> {
> - if (IS_GEN5(devid))
> - return "ironlake";
> - else if (IS_GEN6(devid))
> - return "sandybridge";
> - else if (IS_IVYBRIDGE(devid))
> - return "ivybridge";
> - else if (IS_HASWELL(devid))
> - return "haswell";
> - else if (IS_BROADWELL(devid))
> - return "broadwell";
> - else if (IS_SKYLAKE(devid))
> - return "skylake";
> - else if (IS_KABYLAKE(devid))
> - return "kabylake";
> - else if (IS_CHERRYVIEW(devid))
> - return "cherryview";
> - else if (IS_VALLEYVIEW(devid))
> - return "valleyview";
> -
> - return NULL;
> + return intel_device_info(devid)->codename;
> }
>
> /*
> --
> 2.8.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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