Hello everyone! I need to update the riscv-gnu-toolchain to recognize new custom instructions with two destination registers (starting with the R4 format where rs3 is used as the write register/second destination register). My goal is to obtain hex/bin files for use in a 32-bit custom RISC-V processor that supports those custom instructions. So, the hex/bin files generated must contain the correct encodings of my instructions in order to take advantage of the dedicated hardware in the processor. I am following this strategy: 1. git clone --recursive https://github.com/pulp-platform/riscv-gnu-toolchain.git (probably not the most up-to-date version) 2. configuration with rv32imf (for R4 format support) and --enable-multilib and build the entire toolchain in the /home/name/project1/riscv-gnu-toolchain folder 3. binutils modifications: adding mask, match, and declare for my instructions in riscv-opc.h and defining my instructions and registers used in riscv-opc.c (in this case I use a d,s,t,d syntax to indicate the two destination registers “d”) 4. at this point, given also the solution to other similar issues, the changes should be finished and then I recompile the toolchain (it always takes a while). At this point I get the following error from the assembler: Assembler messages: Error: internal: bad RISC-V opcode (bits 0xf80000 undefined or invalid): cust1 d,s,t,d Fatal error: internal: broken assembler. No assembly attempted Internal error (Segmentation fault). Please report this bug. It would appear that the bits associated with the rs3 register (31..27) are not recognized correctly. I am also wondering if it is possible to achieve my goal by only modifying the binutilis (riscv-opc.h and riscv-opc.c), without modifying other parts of the binutils or gcc to define the correct format (riscv.md, riscv.h, riscv-dis.c and maybe others). Also, does modifying only binutils involve using inline assembly in the C code to specify input and output registers and full encoding with “.word”, or are there similar strategies that allow the compiler to recognize the custom instruction without using inline and without modifying the gcc backend? I would be ready to also modify riscv.md or other files in gcc to achieve my purpose, however at the moment I do not know if it is necessary. I am open to advice and alternative solutions. Thank you Claudio
