On Thu, 2024-01-18 at 17:17 +0100, stefan@xxxxxxxxx wrote: > > -----Ursprüngliche Nachricht----- > > Von: Gcc-help <gcc-help-bounces+bebbo=bejy.net@xxxxxxxxxxx> Im Auftrag > > von Oleg Endo > > Gesendet: Donnerstag, 18. Januar 2024 00:33 > > An: stefan@xxxxxxxxx; gcc-help@xxxxxxxxxxx > > Betreff: Re: AW: autoinc / postinc not used > > > > > > On Wed, 2024-01-17 at 16:19 +0100, stefan@xxxxxxxxx wrote: > > > > > > > > > There are some more hacks needed to fix the handling here and there, most > > work is needed for -funroll-loops. After all, gcc creates beautiful code as > > shown here http://franke.ms/cex/z/MGTb5P . There it's still the old version > > 6.5.0, but maybe I'll port that to a more recent version. > > > If there is interest for other targets, I can provide the information to apply > > my changes. Or you grab it yourself from my github repo. > > > > > > > > > > The results you're getting on GCC 6 look great. Where is the patch or your > > github repo? > > > > Cheers, > > Oleg > > My gcc repo is here: https://github.com/bebbo/gcc and the most important branch is amiga6. Some changes are inside ifdef blocks with TARGET_M68K or TARGET_AMIGAOS. So don't expect to benefits out of the box... > ... > > Nice, although a bit difficult to distill the actual changes. It's better to send a patch to gcc-patches or start a discussion for the anticipated changes at the gimple level on the development mailing list. I've tried to do something for addressing mode optimizations myself + Erik Varga some years ago. https://github.com/erikvarga/gcc/ The idea was to do it solely at RTL level. Original first target was SH, but I had M68K on the radar as well. Actually many other targets would benefit from this. E.g. AFAIK, RISC-V backend has rolled their own way of optimizing for the short displacement. It's a bit difficult to come up with a generic and yet easy to use optimization pass that just magically works. Let me know if you're interested in picking up any of it. Cheers, Oleg
