> -----Ursprüngliche Nachricht-----
> Von: Gcc-help <gcc-help-bounces+bebbo=bejy.net@xxxxxxxxxxx> Im Auftrag
>
> Hi,
>
>
> On Tue, 2024-01-16 at 21:02 +0100, stefan@xxxxxxxxx wrote:
> > Hi all,
> >
> >
> >
> > I work a lot with the good old m68k target where post-increment is
> supported, and I was surprised that there almost no post-increments are used
> in the generated code.
> >
> > This simple code:
> >
> >
> >
> > void memclr (int length, long * ptr) {
> >
> > for(;length--;){
> >
> > *ptr++= 0;
> >
> > }
> >
> > }
> >
> >
> >
> > does not use post-increments on AVR or SH. See also
> > https://godbolt.org/z/fTvdv65rr
> >
> >
>
> This issue has been around for a very long time. I guess auto-inc is not
> important enough on modern architectures to be of a major concern.
>
> On SH{1,2,3,4} post-inc is only available for mem stores, not for mem loads.
> SH2A adds support for stores with post-inc. You have to specify "-mb -m2a"
> for that, as the default target of sh-elf is SH1 (-m1). But yeah, it's also not
> utilized in this case.
>
> Cheers,
> Oleg
There are some more hacks needed to fix the handling here and there, most work is needed for -funroll-loops. After all, gcc creates beautiful code as shown here http://franke.ms/cex/z/MGTb5P . There it's still the old version 6.5.0, but maybe I'll port that to a more recent version.
If there is interest for other targets, I can provide the information to apply my changes. Or you grab it yourself from my github repo.
Regards
Stefan
