On 27/11/2023 16:16, Ed Robbins via Gcc-help wrote:
Hello,
I am using gcc-arm-none-eabi with a cortex M7 device, with caches
(data/instruction) enabled. Nested function calls result in a usage fault
because there is no clear cache call for this platform.
I am not sure I understand you here. Are you talking about trying to
use gcc nested function extensions, implemented by trampolines (small
function stubs on the stack)? If so, then the simple answer is - don't
do that. It's a /really/ bad idea. As far as I understand it, these
are a left-over from the way nested functions were originally
implemented in other gcc languages (Pascal, Ada, Modula-2), which now
handle things differently and far more efficiently. Trampolines were a
convenient way to implement nested functions some 30 years ago, before
caches were the norm, before anyone thought about security, before
processors had prefetching, and before people realised what an
appallingly bad idea self-modifying code is.
If you want to use nested functions, use a language that supports nested
functions, such as Ada, or use C++ with lambdas (which are a bit like
nested functions only much better).
Is there a way to provide the required functions without rebuilding gcc? I
have been looking at the source and, as far as I can tell, there is not.
I can think of at least four ways :
1. The SDK for your microcontroller, provided by the manufacturer, will
have headers with cache clear functions.
2. The ARM CMSIS headers - also available from your manufacturer - has
intrinsic functions, including cache clear functions.
3. gcc has a generic "__buitin__clear_cache" function :
<https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#index-_005f_005fbuiltin_005f_005f_005fclear_005fcache>
4. gcc supports the "ARM C Language Extensions", which include cache
control intrinsics:
<https://gcc.gnu.org/onlinedocs/gcc/ARM-C-Language-Extensions-_0028ACLE_0029.html>
<https://developer.arm.com/documentation/ihi0053/latest/>
But there also doesn't look to be a clean way to implement this: It appears
that this is done on an operating system basis, and when running bare metal
it is not clear where the code would live.
There is no "clean" way to handle the appropriate cache invalidation,
because there is no clean way to get the addresses you need for
invalidating the instruction cache. (Cleanly invalidating the
instruction cache for other purposes, such as during firmware upgrades,
is no problem.)
There are also at least two approaches to solve it, I guess:
1. Somehow indicate on the command line (via target or a dedicated option)
to emit the clear cache call for cortex M, and I guess that the function
itself should do nothing if both caches are disabled.
2. Define hooks or provide a command line option so that developers can
provide an implementation for their platform?
Assuming I were to do this the improper way (and just create a build that
works only for my particular target): Where should I define
CLEAR_INSN_CACHE?
I am not sure if there is already a way to do all this that I am just
unaware of?
Seriously - don't use nested functions in C. Even if you get them
working, it would be painfully inefficient. You'd have to flush parts
of the data cache (to make sure the stack data is written out to main
memory), taking time. You'd then have to invalidate the relevant parts
of the instruction cache. (Even calculating what parts of these caches
to clear will take time and effort.) Then everything needs to be read
into the caches again to actually execute the function.
And what's the point? So that you can write :
void foo(...) {
int bar(...) {
...
}
bar();
}
instead of
static int foo_bar(...) {
...
}
void foo(...) {
foo_bar();
}
or
void foo(...) {
auto bar = [](...) {
...
}
bar();
}
?
