Re: problem on modifying gcc backend for riscv

[Faisal Riyaz <faisalriyaz011@xxxxxxxxx>]

Thanks Segher.

I tried this:

(define_expand "mul<mode>3"
  [(match_operand:ANYF               0 "register_operand" "=f")
(match_operand:ANYF    1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")]
  "TARGET_HARD_FLOAT"
{
rtx reg = gen_reg_rtx (SImode);
emit_insn(gen_mod<mode>floatmul(operands[0], operands[1], operands[2]));
if( fpexception == 3)
{ emit_insn(gen_riscv_frflags(reg));}
DONE;
})

(define_insn "mod<mode>floatmul"
  [(set (match_operand:ANYF               0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF    1 "register_operand" " f")
     (match_operand:ANYF 2 "register_operand" " f")))]
  "TARGET_HARD_FLOAT"
  "fmul.<fmt>\t%0,%1,%2"
  [(set_attr "type" "fmul")
   (set_attr "mode" "<UNITMODE>")])

Now it works fine. Build is successful.

Earlier i think i was <fmt> without using ANYF iterator.



On Sat, Jul 13, 2019 at 6:27 PM Segher Boessenkool <
segher@xxxxxxxxxxxxxxxxxxx> wrote:

> On Sat, Jul 13, 2019 at 09:53:44AM +0530, Faisal Riyaz wrote:
>
> You'll have to do something like
> > (define_insn "modfloatmul<mode>"
>
> and then expand with
>
>   if (<MODE>mode == SFmode)
>     gen_modfloatmulsf (operands[0], operands[1], operands[2]);
>   else if (<MODE>mode == DFmode)
>     gen_modfloatmuldf (operands[0], operands[1], operands[2]);
>   else
>     gcc_unreachable ();
>
>
> Segher
>