On Tue, Jun 25, 2019 at 3:16 AM Faisal Riyaz <faisalriyaz011@xxxxxxxxx> wrote: > How can i make RISC-V generate traps for floating point exceptions? The base ISA does not require traps on FP instructions, but you can build hardware that does if you want. If the hardware does not automatically raise exceptions itself, then the compiler is not going to help you. At present, I don't know of any linux capable hardware that will automatically raise exceptions, and in glibc, feenableexcept gives a linker error saying it is not implemented and will always fail. Or you can add code to your programs to check for exceptions and raise them, e.g. #include <fenv.h> #include <signal.h> feclearexcept (FE_ALL_EXCEPT); ... if (fetestexcept (FE_ALL_EXCEPT)) raise (SIGFPE); though you may not want to raise an exception on FE_INEXACT. You can put this in a macro, sprinkle it through your code, and use another macro to enable/disable it. Jim