On 03/31/2017 09:09 AM, Maxim Blinov wrote:
Hi,
I am configuring a GCC backend for my CPU architecture. However, I am
uncertain as to what I should define the `BASE_REG_CLASS` macro to.
Macro: BASE_REG_CLASS
A macro whose definition is the name of the class to which a valid
base register must belong. A base register is one used in an address
which is the register value plus a displacement.
So, I understand that this macro should return a class of registers
which may appear in instructions of the following form:
`move *(%reg + $offset), %reg`
My architecture only permits register dereferencing with no offset,
apart from the stack register. My questions are:
Should I consequently define the BASE_REG_CLASS macro to return the
stack pointer register class, and second...
I would define BASE_REG_CLASS to be any register that can be used for
simple indirect addressing (that's the same as base+index with a zero
index) and the stack pointer. It may not matter much in the end though.
What is the consequence of having no general registers be capable of
being dereferenced with an immediate offset, in terms of the
implementation-specific code that I would need to add, alongside the
standard assortment of machine description files?
I think we've supported ports with similar restrictions in the past
(ia64?). My biggest worry would be in trying to still allow sp+offset.
You might consider not allowing sp+offset initially until you've got
things mostly working, then look at allow sp+offset in limited cases to
improve the generated code.
jeff
