On 7/14/16, Marc Glisse <marc.glisse@xxxxxxxx> wrote: > On Thu, 14 Jul 2016, Jonathan Wakely wrote: > >> On 14 July 2016 at 01:05, Roger Pack wrote: >>> Hello. >>> As a note after a discussion [1] >>> >>> I ran into this oddness: >>> >>> >>> $ gcc-6 -march=native -Q --help=target | grep march >>> -march= ivybridge >>> $ gcc-6 -march=native -Q --help=target | grep sse3 >>> -msse3 [enabled] >>> -mssse3 [enabled] >>> $ gcc-6 -march=ivybridge -Q --help=target | grep sse3 >>> -msse3 [disabled] >>> -mssse3 [disabled] >>> >>> It appears that specifying (in this case) "-march=ivybridge" which is >>> the native, isn't enough/the same as specifying -march=native? >>> In addition, the "cache sizes" don't seem to be called out with >>> "-march=ivybridge" as they are with "-march=native" >>> Anybody know what I'm missing here? >> >> The named arch is a pre-configured set of supported instructions, >> which should be true for all processors in that range. >> >> Whereas "native" probes the CPU flags and enables precisely the set of >> instructions it supports. >> >> That they are different suggests either the preconfigured settings for >> ivybridge are wrong, or not all processors in that family support all >> the instructions your particular model supports. >> >> Ivybridge should enable SSE3 and SSSE3 though, so I'm nto sure what's >> happening there. > > Option reporting is not reliable. Try preprocessing a file that contains > the macro __SSE3__ to check if sse3 is enabled. > OK that makes more sense thank you. can anyone confirm or deny if the cache-size and cache-line-size are set "appropriately" if cc1 receives the "-march" flag for a particular processor?
