Here is the C code that I used ...
#include <stdio.h>
// NVIC Interrupt Set-Enable Registers
#define NVIC_ISER0 0xE000E100
#define NVIC_ISER1 0xE000E104
#define NVIC_ISER2 0xE000E108
#define NVIC_ISER3 0xE000E10C
#define NVIC_ISER4 0xE000E110
#define NVIC_ISER5 0xE000E114
#define NVIC_ISER6 0xE000E118
#define NVIC_ISER7 0xE000E11C
//reset values
#define RESET 0x00000000
//status flag
#define GOOD 0x600DC0DE
#define DEAD 0xDEADC0DE
#define BAD 0xBAADC0DE
void check_reset_value(int addr, int reset, int status){
asm volatile(
"ldr r2, =8 /* number of register */ \n\t"
"ldr r1, =%0 /* load the nvic_iser* register */ \n\t"
"read_reg:\n\t"
"sub r2, r2, #1\n\t"
"ldr r0, [r1]\n\t"
"add r1, r1, #4 /* go to the next register */ \n\t"
"cmp r0, %1\n\t"
"beq read_reg_ok\n\t"
"ldr r3, =%2\n\t"
"str r3, [%4] /* update status flag */\n\t"
"read_reg_ok:\n\t"
"cmp r2, #0\n\t"
"bne read_reg\n\t"
"ldr r3, =%3\n\t"
"str r3, [%4] /* update status flag */\n\t"
:
: "r" (addr), "r" (reset), "r" (BAD), "r" (GOOD), "r" (status)
//: "r0", "r1", "r2", "r3"
//:
);
}
int main() {
volatile int nvic_iser_status = DEAD;
check_reset_value(NVIC_ISER0, RESET, nvic_iser_status);
}
This is on cortex-m3, so I'm passing -mthumb -mcpu=cortex-m3 to the compiler
On Mon, Jun 10, 2013 at 5:31 PM, Ian Lance Taylor <iant@xxxxxxxxxx> wrote:
>> From: Kalai Rajah N <kalairajah@xxxxxxxxx>
>> Date: Mon, Jun 10, 2013 at 5:19 PM
>> Subject: Re: Thumb inline assembly
>> To: Ian Lance Taylor <iant@xxxxxxxxxx>
>>
>>
>> If the clobber-list is removed, the errors are on r1,r2, r3 and the
>> generated assembly code is ...
>
> When you clobber r0 through r3 they can't be used as input registers.
>
> I still haven't seen a complete standalone test case, but perhaps GCC
> is in ARM mode but you are generating Thumb assembly code.
>
> Ian
