Re: Bit field ordering on Big-Endian (SPARC) processor

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On Tuesday 11 of December 2012 09:12:09 Holmes.Sherlock wrote:
> Paweł Sikora-2 wrote
> > iirc, the C language gives no guarantee of the ordering of fields within
> > machine words,
> > so if you use them for the h/w register modeling, you program will not
> > only be nonportable,
> > it will be compiler-dependent too. you should really read suitable
> > byte/word/doubleword
> > from mapped h/w memory, convert it with le/be_to_cpu() method and
> > shift/mask to access bits.
> 
> But here __attribute__ ((__packed__)) has been used. Doesn't it have any
> effect? Or are we missing out the ordering compiler is enforcing?

gcc's 'packed' attribute is related to the memory usage only.
ordering is still compiler specific.

> Isn't it surprising that on Little Endian system the ordering is as we expect,
> while in Big-Endian system, no apparent correlation is being found?

nothing should be surprising in the times when ARM cores could work in both modes :)

btw.
there's a thread about different ordering @ http://gcc.gnu.org/ml/gcc/2012-10/msg00016.html




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