Hi,
I'm working with MIPS32r2(24kc) and encountered some performance
problems with the code gcc generates.
I have noticed that gcc does not utilize $t[0:9] mips registers
intensively. Instead it's saving several $sX and using them.
Here's is an example of C code and generated asm:
===
void port_handle_exception(uint32_t cause, uint32_t status) {
uint32_t ex = (cause >> 2) & 0x1f;
if (0 == ex) { /* IRQ */
uint32_t ip = ((cause & status) >> 10) & 0x3F; /* only masked IRQs */
while (ip) {
uint32_t i = 31 - __builtin_clz(ip);
if (hw_irq_table[i])
hw_irq_table[i]();
ip &= ~(1 << i);
}
} else
PANIC("unhandled exception");
}
===
800003f4 <port_handle_exception>:
800003f4: 7c822080 ext v0,a0,0x2,0x5
800003f8: 54400024 bnezl v0,8000048c <port_handle_exception+0x98>
800003fc: 3c048001 lui a0,0x8001
80000400: 27bdffd8 addiu sp,sp,-40
80000404: afb00010 sw s0,16(sp)
80000408: 00a48024 and s0,a1,a0
8000040c: 7e102a80 ext s0,s0,0xa,0x6
80000410: afbf0024 sw ra,36(sp)
80000414: afb40020 sw s4,32(sp)
80000418: afb3001c sw s3,28(sp)
8000041c: afb20018 sw s2,24(sp)
80000420: 12000012 beqz s0,8000046c <port_handle_exception+0x78>
80000424: afb10014 sw s1,20(sp)
80000428: 3c148001 lui s4,0x8001
8000042c: 2694b064 addiu s4,s4,-20380
80000430: 2413001f li s3,31
80000434: 24120001 li s2,1
80000438: 72118820 clz s1,s0
8000043c: 02718823 subu s1,s3,s1
80000440: 00111080 sll v0,s1,0x2
80000444: 02821021 addu v0,s4,v0
80000448: 8c420000 lw v0,0(v0)
8000044c: 10400003 beqz v0,8000045c <port_handle_exception+0x68>
80000450: 02328804 sllv s1,s2,s1
80000454: 0040f809 jalr v0
80000458: 00000000 nop
8000045c: 00118827 nor s1,zero,s1
80000460: 02118024 and s0,s0,s1
80000464: 1600fff5 bnez s0,8000043c <port_handle_exception+0x48>
80000468: 72118820 clz s1,s0
8000046c: 8fbf0024 lw ra,36(sp)
80000470: 8fb40020 lw s4,32(sp)
80000474: 8fb3001c lw s3,28(sp)
80000478: 8fb20018 lw s2,24(sp)
8000047c: 8fb10014 lw s1,20(sp)
80000480: 8fb00010 lw s0,16(sp)
80000484: 03e00008 jr ra
80000488: 27bd0028 addiu sp,sp,40
8000048c: 08000175 j 800005d4 <PANIC>
80000490: 24849da0 addiu a0,a0,-25184
===
Instead of using s[0:4] it could easily allocate t[0:4].
Is that a regression(I tried 4.5-4.7) or a well-known limitation?
Any gcc option to force gcc use temp regs(not found in mips-specific options)?
To be precise this function is called directly from asm. However I see
that temp regs are not very intensively utilized globally in the
application.
Thanks and best regards,
-- dmytro
