Hello Ian,
>> Looking at this, it looks like the addition modifies both r1 and r0.
>> This implies that your registers hold HImode values, so the modification
>> to r1 changes the SImode in r0.
I am sorry I should have mentioned register sizes earlier itself.
CR16 has R0-R11 as 16bit registers and R12-R15 as 32 bit registers. For SI
modes, registers pairs of 16 bit registers are used.
I am working on GCC-4.5.1.
In the application's IRA dump, we can see between insns 1605 and 2945, two
register pairs in SI mode, (r1,r0) and (r2,r1) are being used concurrently
for two different purposes. A pair is referred as a single SI mode
register with lower register number i.e. First pair is referred with just R0
and second pair with just R1. As two register numbers appear different to
compiler, it doesn't feel they are overlapping in any way, which is not true
for SI mode. As a result, these 2 pairs get one overlapping register 'r1'.
>> If that is why your instruction sequence is wrong, then are you certain
>> that the value of HARD_REGNO_NREGS is correct?
I checked 'HARD_REGNO_NREGS' macro. It is working fine.
While reading some previous archives, I found that few other architectures
had faced register allocation problem with IRA phase. Therefore I tried to
tweak the IRA_COVER_CLASSES macro in my port. Initially it was defined as:
#define IRA_COVER_CLASSES \
{ \
GENERAL_REGS, LIM_REG_CLASSES \
}
When I split the GENERAL_REGS in following way, it solved my problem.
#define IRA_COVER_CLASSES \
{ \
SHORT_REGS, LONG_REGS, LIM_REG_CLASSES \
}
Now compiler is generating following assembly code:
addd $-2, (sp)
.LCFI547:
movd $18, (r2,r1)
addd (sp), (r2,r1)
push $2,r1
.LCFI548:
movd (r8,r7), (r1,r0)
addd $3, (r1,r0)
As can be seen here, though same overlapping register pairs are being used
here, between the first push and next addd instruction, compiler generates a
load instruction to load the (r1,r0) contents again.
Thanks and Regards,
Jayant Sonar
[KPIT Cummins, Pune]
